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Part: HY5V58BLF-H
Category:
Memory
-> DRAM
-> SDR SDRAM
-> 256 Mb
Description:
Company: Hynix Semiconductor
Datasheet: Download HY5V58BLF-H datasheet File size : 908 kB
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Datasheet text preview:
HY5V58B(L)F
4Banks x 8M x 8bits Synchronous DRAM
DESCRIPTION
The Hynix HY5V58B(L)F is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY5V58B(L)F is organized as 4banks of 8,388,608x8. HY5V58B(L)F is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
· · · · Single 3.3±0.3V power supply All device Balls are compatible with LVTTL interface 54Ball FBGA With 0.8mm of ball pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM · · Internal four banks operation Programmable CAS Latency ; 2, 3 Clocks · · · Auto refresh and self refresh 8192 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full Page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst ·
ORDERING INFORMATION
Part No.
HY5V58BF-H HY5V58BF-8 HY5V58BF-P HY5V58BF-S HY5V58B(L)F-H HY5V58B(L)F-8 HY5V58B(L)F-P HY5V58B(L)F-S
Clock Frequency
133MH z 125MHz 100MH z 100MH z 133MHz 125MHz 100MH z 100MH z
Power
Organization
Interface
Package
Normal
4Banks x 8Mbits x8 Low power
LVTTL
54ball FBGA
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1/Apr. 02 2
HY5V58B(L)F
BALL CONFIGURATION
9 8 7 3 2 1
A B C D E F G H J
1 VSS NC NC NC NC DQM A12 A8 VSS 2 DQ7 DQ6 DQ5 DQ4 NC CLK A11 A7 A5 3 VSSQ VDDQ VSSQ VDDQ VSS CK E A9 A6 A4 A B C D E F G H J 7 VDD Q VSSQ VDD Q VSSQ VDD /CAS B A0 A0 A3 8 DQ0 DQ1 DQ2 DQ3 NC /RAS B A1 A1 A2 9 VDD NC NC NC NC /WE /CS A10 VDD
54 Ball FBGA 0.8 mm Ball Pitch
Rev. 0.1/Apr. 02 3
HY5V58B(L)F
Ball DESCRIPTION
Ba ll C LK C KE CS BA0, BA1 A0 ~ A12 Clock Clock Enable Chip Select Bank Address A dd ress Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection Ball NAME DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE and DQM Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA9 Auto-precharge flag : A10 RAS, CAS and WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output Ball Power supply for internal circuits and input buffers Power supply for output buffers No connection
RAS, CAS, WE DQM DQ0 ~ DQ7 V D D /V S S VDDQ/VSSQ NC
Rev. 0.1/Apr. 02
4
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