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Part: HY5V56BLF-SI
Category:
Memory
-> DRAM
-> SDR SDRAM
-> 256 Mb
Description:
Company: Hynix Semiconductor
Datasheet: Download HY5V56BLF-SI datasheet File size : 908 kB
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Datasheet text preview:
HY5V56B(L/S)F-I Series
4 Banks x 4M x 16bits Synchronous DRAM
Preliminary DESCRIPTION
The HY5V56B(L)F is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the Mobile applications which require low power consumption and industrial temperature range. HY5V56B(L)F is organized as 4banks of 4,194,304x16 HY5V56B(L)F is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
· · · · Single 3.3±0.3V power supply All device balls are compatible with LVTTL interface 54Ball FBGA (13.5mm x 8.0mm) All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM or LDQM · · Internal four banks operation Programmable CAS Latency ; 2, 3 Clocks · · · Auto refresh and self refresh 8192 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst ·
ORDERING INFORMATION
Part No.
HY5V56BF-HI H Y 5V56BF-8 I HY5V56BF-PI HY5V56BF-SI HY5V56B(L)F-HI H Y 5 V 5 6 B ( L) F - 8I HY5V56B(L)F-PI HY5V56B(L)F-SI
Clock Frequency
133MHz 125MHz 100MHz 100MHz 133MHz 125MHz 100MHz 100MHz
Power
Organization
Interface
Package
Normal
4Banks x 4Mbits x16 Low power
LVTTL
54ball FBGA
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1/Sep. 02
HY5V56B(L/S)F-I
BALL CONFIGURATION
9 8 7 3 2 1
A B C D E F G H J
1 VSS DQ14 DQ12 DQ10 DQ8 UDQM A12 A8 VSS 2 DQ15 DQ13 DQ11 DQ9 NC CLK A11 A7 A5 3 VSSQ VDDQ VSSQ VDDQ VSS CK E A9 A6 A4 A B C D E F G H J 7 VDD Q VSSQ VDD Q VSSQ VDD /CAS B A0 A0 A3 8 DQ0 DQ2 DQ4 DQ6 LDQM /RAS B A1 A1 A2 9 VDD DQ1 DQ3 DQ5 DQ7 /WE /CS A10 VDD
54 Ball FBGA 0.8 mm Ball Pitch
Rev. 0.1/Sep. 02 3
HY5V56B(L/S)F-I
BALL DESCRIPTION
BALL OUT F2 F3 SYMBOL CLK CK E T YPE INPUT INPUT DESCRIPTION Clock : The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Clock Enable : Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Chip Select : Enables or disables all inputs except CLK, CKE, UDQM and LDQM Bank Address : Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8 Auto-precharge flag : A10
G9 G7,G8
CS BA0, BA1
INPUT INPUT
H7, H8, J8, J7, A0 ~ A12 J3, J2, H3, H2, H1, G3, H9, G2, G1 F8, F7, F9 F1, E8 A8, B9, B8, C9, C8, D9, D8, E9, E1, D2, D1, C2, C1, B2, B1, A2 A9, E7, J9, A1, E3, J1 A7, B3, C7, D3, A3, B7, C3, D7 E2, G1 RAS, CAS, WE UD QM, LDQM DQ0 ~ DQ15
INPUT
INPU T INPUT I/O
Command Inputs : RAS, CAS and WE define the operation Refer function truth table for details Data Mask:Controls output buffers in read mode and masks input data in write mode Data Input/Output:Multiplexed data input/output ball
VDD/VSS VDDQ/ VSS Q NC
SUPPLY SUPPLY -
Power supply for internal circuits Power supply for output buffers No connection
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