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Part: HY5PS121621F
Category:
Memory
-> DRAM
-> DDR2 SDRAM
-> 512 Mb
Description:
Company: Hynix Semiconductor
Datasheet: Download HY5PS121621F datasheet File size : 908 kB
Request For quote: Find where to buy HY5PS121621F
Datasheet text preview:
HY5PS12421(L)F HY5PS12821(L)F HY5PS121621(L)F
512Mb DDR2 SDRAM
HY5PS12421(L)F HY5PS12821(L)F HY5PS121621(L)F
Rev. 0.6 / Apr.2003
1
HY5PS12421(L)F HY5PS12821(L)F HY5PS121621(L)F REVISION HISTORY
Rev. No. 0.2 0.3 0.4 0.5 0.51 0.52 0.53 0.6 Rev. Date Jun.2002 July.2002 Aug.2002 Aug.2002 Oct.2002 Nov.2002 Dec.2002 Apr.2003 Page1,6,7,29 Page9,10 Page of Rev. page3 All All All Page7,52 Description of Change added tCK on the operating frequency table Changed master page corrected typos and change some descriptions corrected typos and wrong definiotions and changed some items page7:modify Package Dimension, page52 change TA to TC, etc. corrected typos, Add x16 part and update Package dimensions corrected typos and delete page29 tRAS programming definition Changed Package dimensions Changed Part Number Added 667 Speed bin
Rev. 0.6 / Apr.2003
2
HY5PS12421(L)F HY5PS12821(L)F HY5PS121621(L)F KEY FEATURES
· · · · · · · · · · · · · · · · · · · · · · · VDD = 1.8V, 2.5V (Optional) VDDQ = 1.8V +/- 0.1V All inputs and outputs are compatible with SSTL_18 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS, DQS) Differential Data Strobe (DQS, DQS) Data outputs on DQS, DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL align DQ, DQS and DQS transition with CK transition DM mask write data-in at the both rising and falling edges of the data strobe All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock Programmable CAS latency 3, 4 and 5 supported Programmable Additive latency 0, 1, 2, 3, 4 and 5 supported Programmable burst length 4 / 8 with both nibble sequential and interleave mode Internal four bank operations with single pulsed RAS Auto refresh and self refresh supported Programmable tRAS supported 8K refresh cycles / 64ms JEDEC standard 60ball FBGA(x4/x8) & 84bal FBGA(x16)l Full strength driver option controlled by EMRS On Die Termination supported Off Chip Driver Impedance Adjustment supported Read Data Strobe supported (x8 only)
Preliminary
ORDERING INFORMATION
Part No. HY5PS12421(L)F-X* HY5PS12821(L)F-X* HY5PS121621(L)F -X* Configuration 128Mx4 64Mx8 32Mx16 Packag e 60 Ball FBGA 84Ball FBGA
OPERATING FREQUENCY
Grade -E3 -E4 -C4 -C5 -Y5 -Y6 tCK(ns) 5 5 3. 75 3. 75 3 3 CL 3 4 4 5 5 6 tRCD 3 4 4 5 5 6 tRP 3 4 4 5 5 6 Unit Clk Clk Clk Clk Clk Clk
* X means speed grade
Rev. 0.6 / Apr.2003
3
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