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Part: HY5DV641622AT-43
Category:
Memory
-> DRAM
-> DDR SDRAM
-> 64 Mb
Description:
Company: Hynix Semiconductor
Datasheet: Download HY5DV641622AT-43 datasheet File size : 908 kB
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Datasheet text preview:
HY5DV641622AT
64M(4Mx16) DDR SDRAM
HY5DV641622AT
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.7/May. 02 1
HY5DV641622AT
Revision History
4. Revision 0.7 (May. 02)
1) Input leakage current changed from +/-5uA to +/-2uA
3. Revision 0.6 (Dec. 01)
1) Separated `Function description' and `Timing diagram' parts - These are available in Web site (www.hynix.com)
2. Revision 0.5 (Nov. 01)
1) Changed tCK maximum value a) 300/275Mhz : Changed from 4.5ns to 4.0ns b) 250/200Mhz : Changed from 8.0ns to 6.5ns 2) Changed `VDDQ range' from +/- 0.2V to +/- 5% - Changed from 2.3V/2.5V/2.7V to 2.375V/2.5V/2.625V (min/typ/max)
1. Revision 0.4 (Sep. 01)
1) Removed 183/166Mhz parts from speed bin 2) Changed Cas Latency from 3 to 4 at 300/275Mhz 3) Changed tRCD from 5clk to 6clk at 300/275Mhz 4) Changed tCK maximum value from 8ns to 4.5ns at 300/275Mhz 5) Changed VDD value a) 275Mhz : Changed from 3.15V/3.30V/3.45V to 3.20V/3.30V/3.45V (min/typ/max) b) 300Mhz : Changed from 3.15V/3.30V/3.45V to 3.35V/3.45V/3.55V (min/typ/max) 6) Modified `Burst Read followed by Burst Write' function - Burst Write command must be issued after (CL + BL/2 + 1) ticks of clock from Burst Read command, not (CL + BL/2) ticks of clock at 300/275Mhz
Rev. 0.7/May. 02
2
HY5DV641622AT DESCRIPTION
The Hynix HY5DV641622 is a 67,108,864-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point-to-point applications which requires high bandwidth. The Hynix 4Mx16 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2.
FEATURES
· · · · · · · · 3.3V for VDD and 2.5V for VDDQ power supply All inputs and outputs are compatible with SSTL_2 interface JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has 2 bytewide data strobes (LDQS, UDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) Data(DQ) and Write masks(DM) latched on the both rising and falling edges of the data strobe · · · · · · · · · All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock Write mask byte controls by LDM and UDM Programmable /CAS Latency 3 / 4 supported Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode Internal 4 bank operations with single pulsed /RAS tRAS Lock-Out function supported Auto refresh and self refresh supported 4096 refresh cycles / 64ms Full, Half and Matched Impedance(Weak) strength driver option controlled by EMRS
·
ORDERING INFORMATION
Part No. HY5DV641622AT-33 HY5DV641622AT-36 HY5DV641622AT-4 HY5DV641622AT-5 VDD=3.3V VDDQ=2.5V Power Supply Clock Frequency 300MHz 275MHz 250MHz 200MHz Max Data Rate 600Mbps/pin 550Mbps/pin 500Mbps/pin 400Mbps/pin SSTL_2 400mil 66pin TSOP-II interface Package
Rev. 0.7/May. 02
3
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