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Part: HY5DU283222AF-36
Category:
Memory
-> DRAM
-> DDR SDRAM
-> 128 Mb
Description:
Company: Hynix Semiconductor
Datasheet: Download HY5DU283222AF-36 datasheet File size : 908 kB
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Datasheet text preview:
HY5DU283222AF
128M(4Mx32) DDR SDRAM
HY5DU283222AF
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.3/Mar. 03 1
HY5DU283222AF
Revision History
4. Rev 0.3 (Mar. 03)
1) Added 222MHz with CL3 and tCK_max=10ns at HY5DU283222AF-36 2) Changed VDD_min value of HY5DU283222AF-36 from 2.375V to 2.2V 3) Changed AC parameters value of HY5DU283222AF-28/33 - tRCDRD/tRP : from 6 tCK to 5 tCK - tDAL : from 9 tCK to 8 tCK - tRFC : from 19 tCK to 17 tCK 4) Changed IDD2N target specification 5) Changed tCK_max value of HY5DU283222AF-33/36 from 6ns to 10ns
3. Rev 0.2 (Feb. 03)
1) Defined IDD specification
2. Rev 0.11 (Dec. 02)
1) 500MHz speed bin added
1. Rev 0.1 (Nov. 02)
1) Defined target spec.
Rev. 0.3/Mar. 03
2
HY5DU283222AF DESCRIPTION
PRELIMINARY
The Hynix HY5DU283222 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point-to-point applications which requires high bandwidth. The Hynix 4Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2.
FEATURES
· · · · · · · · 2.5V +/- 5% VDD and VDDQ power supply supports 300/275/250MHz 2.8V +/- 5% VDD and VDDQ power supply supports 500/450/400/350MHz All inputs and outputs are compatible with SSTL_2 interface 12mm x 12mm, 144ball FBGA with 0.8mm pin pitch Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS0 ~ DQS3) Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) · · · · · · · Data(DQ) and Write masks(DM) latched on the both rising and falling edges of the data strobe All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock Write mask byte controls by DM (DM0 ~ DM3) Programmable /CAS Latency 5, 4 and 3 supported Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode Internal 4 bank operations with single pulsed /RAS tRAS Lock-Out function supported Auto refresh and self refresh supported 4096 refresh cycles / 32ms Half strength and Matched Impedance driver option controlled by EMRS
· · ·
ORDERING INFORMATION
Part No. HY5DU283222AF-2 HY5DU283222AF-22 HY5DU283222AF-25 HY5DU283222AF-28 HY5DU283222AF-33 HY5DU283222AF-36
Rev. 0.3/Mar. 03
Power Supply
Clock Frequency 500MHz
Max Data Rate 1000Mbps/pin 900Mbps/pin 800Mbps/pin 700Mbps/pin 600Mbps/pin 550Mbps/pin
interface
Package
VDD 2.8V VDDQ 2.8V
450MHz 400MHz 350MHz
SSTL_2
12mm x 12mm 144Ball FBGA
VDD 2.5V VDDQ 2.5V
300MHz 275MHz
3
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