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Part: HY57V643220CT-5
Category:
Memory
-> DRAM
-> SDR SDRAM
-> 64 Mb
Description:
Company: Hynix Semiconductor
Datasheet: Download HY57V643220CT-5 datasheet File size : 931 kB
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Datasheet text preview:
HY57V643220C
4 Banks x 512K x 32Bit Synchronous DRAM
DESCRIPTION
The Hynix HY57V643220C is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY57V643220C is organized as 4banks of 524,288x32. HY57V643220C is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
JEDEC standard 3.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 86pin TSOP-II with 0.5mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM0,1,2 and 3 Programmable CAS Latency ; 2, 3 Clocks Internal four banks operation Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst
ORDERING INFORMATION
Part No.
HY57V643220C(L)T-43 HY57V643220(L)CT-5 HY57V643220C(L)T-55 HY57V643220C(L)T-6 HY57V643220C(L)T-7 HY57V643220C(L)T-8 HY57V643220C(L)T-P HY57V643220C(L)T-S
Clock Frequency
23 3M H z 20 0MH z 18 3M H z 16 6MH z 14 3MH z 12 5MH z 10 0MH z 10 0MH z
Power
Organization
Interface
Package
Normal/ Low Power
4B an ks x 512Kbits x32
LVT T L
400mil 86pin TSOP II
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.5/Dec. 01 1
HY57V643220C
PIN CONFIGURATION
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 /W E /C A S /R A S /C S NC BA0 BA1 A 1 0 /A P A0 A1 A2 DQM2 VDD NC D Q 16 VSSQ D Q 17 D Q 18 VDDQ D Q 19 D Q 20 VSSQ D Q 21 D Q 22 VDDQ D Q 23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS D Q 15 VSSQ D Q 14 D Q 13 VDDQ D Q 12 D Q 11 VSSQ D Q 10 DQ9 VDDQ DQ8 NC VSS DQM1 NC NC C LK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC D Q 31 VDDQ D Q 30 D Q 29 VSSQ D Q 28 D Q 27 VDDQ D Q 26 D Q 25 VSSQ D Q 24 VSS
8 6 p i n T S O P II 4 0 0 m il x 8 7 5 m il 0 . 5 m m p in p itc h
PIN DESCRIPTION
P IN C LK C KE CS BA0, BA1 A0 ~ A10 Clock Clock Enable Chip Select Bank Address Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/ Ground No Connection PIN NAME DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK. Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE and DQM Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7 Auto-precharge flag : A10 RAS, CAS and WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Power supply for output buffers No connection
RAS, CAS, WE
DQM0~3 DQ0 ~ DQ31 V DD / V S S VDDQ/VSSQ NC
Rev. 0.5/Dec. 01
2
HY57V643220C
FUNCTIONAL BLOCK DIAGRAM 512Kbit x 4banks x 32 I/O Synchronous DRAM
Self Refresh Logic & Timer Refresh Counter
CLK CKE CS State Machine RAS CAS WE DQM0 DQM1 DQM2 DQM3
Row Active
512Kx32 Bank 3 Row Pre Decoder 512Kx32 Bank 2 X decoder 512Kx32 Bank 1 X decoder 512Kx32 Bank 0 X decoder DQ0 DQ1 I/O Buffer & Logic Sense AMP & I/O Gate
X decoder
Memory Cell Array
Column Active
Column Pre Decoder Y decoder
DQ30 DQ31
Bank Select
Column Add Counter
A0 A1 Address buffers A10 BA0 BA1
Address Register Burst Counter
Mode Register
CAS Latency
Data Out Control
Pipe Line Control
Rev. 0.5/Dec. 01
3
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