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Part: HY57V561620HLT-6
Category:
Memory
-> DRAM
-> SDR SDRAM
-> 256 Mb
Description:
Company: Hynix Semiconductor
Datasheet: Download HY57V561620HLT-6 datasheet File size : 931 kB
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Datasheet text preview:
HY57V561620H(L)T
4 Banks x 4M x 16Bit Synchronous DRAM
DESCRIPTION
The HY57V561620HT is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V561620HT is organized as 4banks of 4,194,304x16. HY57V561620HT is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
· · · Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM, LDQM Internal four banks operation · · · · Auto refresh and self refresh 8192 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full page for Sequential Burst · - 1, 2, 4 or 8 for Interleave Burst Programmable CAS Latency ; 2, 3 Clocks
· ·
ORDERING INFORMATION
Part No.
HY57V561620HT-6 H Y 5 7 V 5 6 1 6 2 0 H T -K H Y 5 7 V 5 6 1 6 2 0 H T -H HY57V561620HT-8 H Y 5 7 V 5 6 1 6 2 0 H T -P H Y 5 7 V 5 6 1 6 2 0 H T -S HY57V561620HLT-6 HY57V561620HLT-K HY57V561620HLT-H HY57V561620HLT-8 HY57V561620HLT-P HY57V561620HLT-S
Clock Frequency
166M Hz 133M Hz 133M Hz 125M Hz 100M Hz 100M Hz 166M Hz 133M Hz 133M Hz 125M Hz 100M Hz 100M Hz
Power
Organization
Interface
Package
Norm al
4Banks x 4Mbits x16
LVTTL
400mil 54pin TSOP II
Low power
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.3/Nov. 01 1
HY57V561620H(L)T
PIN CONFIGURATION
VD D DQ0 VD D Q DQ1 DQ2 VS SQ DQ3 DQ4 VD D Q DQ5 DQ6 VS SQ DQ7 VD D LD QM /W E /C A S /R A S /C S BA0 BA1 A 1 0 /A P A0 A1 A2 A3 VD D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VS S D Q 15 VS SQ D Q 14 D Q 13 VD D Q D Q 12 D Q 11 VS SQ D Q 10 DQ9 VD D Q DQ8 VS S NC U D QM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VS S
5 4p in TSOP II 4 00m il x 875mil 0 .8m m pin pitch
PIN DESCRIPTION
PIN CLK CKE CS BA0, BA1 A0 ~ A12 Clock Clock Enable Chip Select Bank Address Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection PIN NAME DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE, UDQM and LDQM Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8 Auto-precharge flag : A10 RAS, CAS and WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Power supply for output buffers No connection
RAS, CAS, WE UDQM, LDQM DQ0 ~ DQ15 VDD/VSS VDDQ/VSSQ NC
Rev. 1.3/Nov. 01
2
HY57V561620H(L)T
FUNCTIONAL BLOCK DIAGRAM
4Mbit x 4banks x 16 I/O Synchronous DRAM
Self Refresh Logic & Timer
Internal Row Counter
CLK
Row Active
4Mx16 Bank 3 Row Pre Decoders 4Mx16 Bank 2 X decoders 4Mx16 Bank 1 X decoders 4Mx16 Bank 0 DQ0 DQ1 I/O Buffer & Logic Sense AMP & I/O Gate
CKE CS State Machine RAS CAS WE UDQM LDQM
X decoders
Memory Cell Array
Column Active
Column Pre Decoders Y decoders
DQ14 DQ15
Bank Select
Column Add Counter
A0 A1 Address buffers A12 BA0 BA1
Address Register Burst Counter
Mode Registers
CAS Latency
Data Out Control
Pipe Line Control
Rev. 1.3/Nov. 01
3
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