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Part: M30627FHPGP
Category:
Microprocessors
-> 16 bit
-> M16C family->M16C/60 series
Description:
Company: Renesas
Datasheet: Download M30627FHPGP datasheet File size : 5104 kB
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Datasheet text preview:
M16C/62 Group (M16C/62P)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
REJ03B0001-0110Z Rev.1.10 2003.05.28
Overview
The M16C/62 group (M16C/62P) of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin and 128-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. In addition, this microcomputer contains a multiplier and DMAC which combined with fast instruction processing capability, makes it suitable for control of various OA, communication, and industrial equipment which requires high-speed arithmetic/logic operations.
Applications
Audio, cameras, office/communications/portable/industrial equipment, etc
Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. Specifications in this manual may be changed for functional or performance improvements. Please make sure your manual is the latest edition.
Rev.1.10
2003.05.28 page 1 of 61
M16C/62 Group (M16C/62P)
Overview
Performance Outline
Table 1.1.1 lists performance outline of M16C/62P group. Table 1.1.1. Performance outline of M16C/62P group Item Performance Number of basic instructions 91 instructions Shortest instruction execution time 41.7 ns (f(BCLK)= 24MHZ, VCC1= 3.0V to 5.5V) 100 ns (f(BCLK)= 10MHZ, VCC1= 2.7V to 5.5V) Memory ROM (See the product list) capacity RAM (See the product list) I/O port 100-pin version 8 bits x 10, 7 bits x 1 P0 to P5: VCC2 ports P6 to P10: VCC1 ports P0 to P10 (except P85) 8 bits x 13, 7 bits x 1, P0 to P5, P12, P13: VCC2 ports 128-pin version P0 to P14 (except P85) 2 bits x 1 _______ P6 to P10, P11, P14: VCC1 ports Input port P8 5 1 bit x 1 (NMI pin level judgment): VCC1 ports Multifunction timer Output 16 bits x 5 channels (TA0, TA1, TA2, TA3, TA4) Input 16 bits x 6 channels (TB0, TB1, TB2, TB3, TB4, TB5) Serial I/O 3 channels (UART0, UART1, UART2) UART, clock synchronous, I2C bus1 (option4), or IEBus2 (option4) 2 channels (SI/O3, SI/O4) Clock synchronous A-D converter 10 bits x (8 x 3 + 2) channels D-A converter 8 bits x 2 DMAC 2 channels (trigger: 25 sources) CRC calculation circuit CRC-CCITT Watchdog timer 15 bits x 1 (with prescaler) Interrupt 29 internal and 8 external sources, 4 software sources, 7 levels Clock generation circuit 4 circuits · Main clock (These circuits contain a built-in feedback · Sub-clock resistor and external ceramic/quartz oscillator) · Ring oscillator(main-clock oscillation stop detect function) · PLL frequency synthesizer Voltage detection circuit Present (option4) Power supply voltage VCC1=3.0V to 5.5V, VCC2=3.0V to VCC1(f(BCLK)=24MHZ) VCC1=VCC2=2.7V to 5.5V (f(BCLK)=10MHZ) Flash memory Program/erase voltage 3.3V ± 0.3V or 5.0V ± 0.5V Number of program/erase 100 times, 10000 times3 (option4) Power consumption 14mA (VCC1=VCC2=5V, f(BCLK)=24MHZ) 8mA (VCC1=VCC2=3V, f(BCLK)=10MHZ) 1.8µA (VCC1=VCC2=3V, f(XCIN)=32kHZ, when wait mode) I/O I/O withstand voltage 5.0V characteristics Output current 5mA Memory expansion Available (to 4M bytes) Operating ambient temperature -20 to 85°C -40 to 85°C (option4) Device configuration CMOS high performance silicon gate Package 100-pin and 128-pin plastic mold QFP
Notes: 1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V. 2. IEBus is a registered trademark of NEC Electronics Corporation. 3. Block 1 and block A are a 10,000 times of programming and erasure. All other blocks are guaranteed of 1,000 times of programming and erasure. (Under development; mass production scheduled to start in the 3rd quarter of 2003) 4. If you desire this option, please so specify. Rev.1.10 2003.05.28 page 2 of 61
M16C/62 Group (M16C/62P)
Overview
Block Diagram
Figure 1.1.1 is a block diagram of the M16C/62P group.
8
8
8
8
8
8
8
Port P0
Port P1
Port P2 Port P3
Port P4
Port P5
Port P6
Port P7
8
Internal peripheral functions
Timer (16-bit) Output (timer A): 5 Input (timer B): 6 Three-phase motor control circuit
A-D converter
(10 bits X 8 channels
Expandable up to 26 channels) UART or clock synchronous serial I/O
System clock generator XIN-XOUT XCIN-XCOUT
PLL frequency synthesizer Ring oscillator
Port P8
7
(8 bits X 3 channels)
CRC arithmetic circuit (CCITT ) (Polynomial : X16+X12+X5+1)
Clock synchronous serial I/O
(8 bits X 2 channels)
Port P85
Watchdog timer
(15 bits)
M16C/60 series16-bit CPU core
R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC
Memory
ROM (Note 1) RAM (Note 2)
Port P9
DMAC
(2 channels)
8
D-A converter
(8 bits X 2 channels)
Port P10
FLG
Multiplier
8
Port P11
(Note 3)
Port P12
(Note 3)
Port P14
(Note 3)
Port P13
(Note 3)
8
2
8
8
Note 1: ROM size depends on microcomputer type. Note 2: RAM size depends on microcomputer type. Note 3: Ports P11 to P14 exist only in 128-pin version.
Figure 1.1.1. Block Diagram
Rev.1.10
2003.05.28
page 3 of 61
Others parts begin by m3
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