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Part: 100336CW
Category:
Logic
-> Counters
-> Bipolar->ECL 100 Family
Description: Low Power 4-Stage Counter/shift Register
Company: Fairchild Semiconductor
Datasheet: Download 100336CW datasheet File size : 369 kB
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Datasheet text preview:
100336 Low Power 4-Stage Counter/Shift Register
August 1989 Revised August 2000
100336 Low Power 4-Stage Counter/Shift Register
General Description
The 100336 operates as either a modulo-16 up/down counter or as a 4-bit bidirectional shift register. Three Select (Sn) inputs determine the mode of operation, as shown in the Function Select table. Two Count Enable (CEP, CET) inputs are provided for ease of cascading in multistage counters. One Count Enable (CET) input also doubles as a Serial Data (D0) input for shift-up operation. For shift-down operation, D3 is the Serial Data input. In counting operations the Terminal Count (TC) output goes LOW when the counter reaches 15 in the count/up mode or 0 (zero) in the count/down mode. In the shift modes, the TC output repeats the Q3 output. The dual nature of this TC/Q3 output and the D0/CET input means that one interconnection from one stage to the next higher stage serves as the link for multistage counting or shift-up operation. The individual Preset (Pn) inputs are used to enter data in parallel or to preset the counter in programmable counter applications. A HIGH signal on the Master Reset (MR) input overrides all other inputs and asynchronously clears the flipflops. In addition, a synchronous clear is provided, as well as a complement function which synchronously inverts the contents of the flip-flops. All inputs have 50 k pull-down resistors.
Features
s 40% power reduction of the 100136 s 2000V ESD protection s Pin/function compatible with 100136 s Voltage compensated operating range = -4.2V to -5.7V s Available to industrial grade temperature range
Ordering Code:
Order Number 100336SC 100336PC 100336QC 100336QI Package Number M24B N24E V28A V28A Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (-40°C to +85°C)
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagrams
24-Pin DIP/SOIC 28-Pin PLCC
Logic Symbol
© 2000 Fairchild Semiconductor Corporation
DS010584
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100336
Function Select Table
S2 L L L L H H H H S1 L L H H L L H H S0 L H L H L H L H Function Parallel Load Complement Shift Left Shift Right Count Down Clear Count Up Hold
Pin Descriptions
Pin Names CP CEP D 0 /CE T S0S2 MR P0P3 D3 TC Q0Q3 Q0Q3 Description Clock Pulse Input Count Enable Parallel Input (Active LOW) Serial Data Input/Count Enable Trickle Input (Active LOW) Select Inputs Master Reset Input Preset Inputs Serial Data Input Terminal Count Output Data Outputs Complementary Data Outputs
Truth Table
Q0 = LSB Inputs Outputs MR S2 S1 S0 CEP D0/CET D3 CP Q3 Q2 Q1 Q0 L L L L L L L L L L L L H H H H H H H H H L L L L H H H H H H H H L L L L H H H H H L L H H L L L L H H H H L L H H L L L H H L H L H L L L H L L L H L H L H L L H L H X X X X L H X X L H X X X X X X X X X X X X X X X L L H X L L H X X X X X L H X X X X X X X X X X X X X X X X X X X X X X X X
X X X X X X X X X
TC L L D3 1 1 H H 2 2 H H L L L L L H H H H
Mode Preset (Parallel Load) Invert Shift to LSB Count Down Count Down with CEP not active Count Down with CET not active Clear Count Up Count Up with CEP not active Count Up with CET not active Hold
P3 P2 P1 P0 Q3 Q2 Q1 Q0 D3 Q3 Q2 Q1 (Q03) minus 1
Q2 Q1 Q0 D0 Q3 (Note 1) Shift to MSB
X Q3 Q2 Q1 Q0 X Q3 Q2 Q1 Q0 L L L L (Q03) plus 1
X Q3 Q2 Q1 Q0 X Q3 Q2 Q1 Q0 X Q3 Q2 Q1 Q0 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L
Asynchronous Master Reset
1 = L if Q0Q3 = LLLL H if Q0Q3 LLLL 2 = L if Q0Q3 = HHHH H if Q0Q3 HHHH H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW-to-HIGH Transition
Note 1: Before the clock, TC is Q3 After the clock, TC is Q2
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100336
Logic Diagram
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100336
Absolute Maximum Ratings(Note 2)
Storage Temperature (TSTG) Maximum Junction Temperature (TJ) VEE Pin Potential to Ground Pin Input Voltage (DC) Output Current (DC Output HIGH) ESD (Note 3)
-65°C to +150°C +150 °C -7.0V to +0.5V
VEE to +0.5V
Recommended Operating Conditions
Case Temperature (TC) Commercial Industrial Supply Voltage (VEE) 0°C to +85°C
-40°C to +85°C -5.7V to -4.2V
-50 mA 2000V
Note 2: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version DC Electrical Characteristics (Note 4)
VEE = -4.2V to -5.7V, VCC = VCCA = GND, TC = 0°C to +85°C Symbol Parameter M in Typ VOH VOL VOHC VOLC VIH VIL IIL IIH IEE Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current Power Supply Current -165 -1165 -1830 0.50 240 -80 -1025 -1830 -1035 -1610 -870 -1475 -955 -1705 Max -870 -1620 Units mV mV mV mV mV mV µA µA VIN =VIH (Max) or VIL (Min) VIN = VIH(Min) or VIL (Max) Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VIN = VIL (Min) VIN = VIH (Max) Inputs Open Conditions Loading with 50 to -2.0V Loading with 50 to -2.0V
Note 4: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under "worst case" conditions.
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100336
Commercial Version (Continued) DIP AC Characteristics
VEE = -4.2V to -5.7V, VCC = VCCA = GND Symbol fSHIFT tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPLH tPHL tPLH tPHL tTLH tTHL tS Parameter Shift Frequency Propagation Delay CP to Qn, Qn Propagation Delay CP to TC (Shift) Propagation Delay CP to TC (Count) Propagation Delay MR to Qn, Qn Propagation Delay MR to TC (Count) Propagation Delay MR to TC (Shift) Propagation Delay D0/CET to TC Propagation Delay Sn to TC Transition Time 20% to 80%, 80% to 20% Setup Time D3 Pn D0/CET CEP Sn MR (Release Time) tH Hold Time D3 Pn D0/CET CEP Sn tPW(H) Pulse Width HIGH CP, MR 0.40 0.30 0.30 0.20 0.10 2.00 0.40 0.30 0.30 0.20 0.10 2.00 0.40 0.30 0.30 0.20 0.10 2.00 ns Figures 3, 4 ns Figure 6 1.00 1.50 1.30 1.40 3.40 2.60 1.00 1.50 1.30 1.40 3.40 2 .60 1.00 1.50 1.30 1.40 3.40 2.60 ns Figures 6, 4 TC = 0°C Min 300 1.00 2.10 2.40 1.40 2.80 2.40 1.80 1.90 0.35 2.00 3.50 4.40 2.50 5.10 4.00 3.10 4.10 1.20 Max TC = +25°C Min 300 1.00 2.10 2.40 1.40 2.90 2.40 1.80 1.90 0.35 2.00 3.50 4.40 2.50 5.20 4.00 3.10 4.10 1.20 Max TC = +85°C M in 300 1.00 2.10 2.60 1.50 3.10 2.50 1.90 2.10 0.35 2.00 3.70 4.70 2.60 5.50 4.10 3.30 4.40 1.20 M ax MHz ns ns ns ns ns ns ns ns ns Figures 2, 3 Figures 1, 3 (Note 5) Figures 1, 7, 8 (Note 5) Figures 1, 9 (Note 5) Figures 1, 4 (Note 5) Figures 1, 12 (Note 5) Figures 1, 10, 11 (Note 5) Figures 1, 5 (Note 5) Units Conditions
Figures 1, 3
Note 5: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching.
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