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Part: EM6621WW11
Category:
Description: Ultra-low Power MCU With Integrated 4x20 LCD Driver0.5mA, 1.2V, 4kx16 ROM
Company: EM Microelectronic
Datasheet: Download EM6621WW11 datasheet File size : 827 kB
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EM6621
Ultra Low Power Microcontroller with 4x20 LCD Driver
Features
· Low Power - 2.6 µA active mode, LCD On - 0.5 µA standby mode, LCD Off - 0.1 µA sleep mode @ 1.5 V, 32 KHz, 20 ºC Low Voltage - 1.2 to 3.6 V 2 clocks per instruction cycle 72 basic instructions ROM 4k x 16 bits RAM 128 x 4 bits Max. 12 inputs ; port A, port B, port SP Max. 8 outputs ; port B, port SP Voltage Level Detector, 8 levels software selectable from 1.2 V up to 4.0 V Melody, 7 tones + silence inclusive 4-bit timer Universal 10-bit counter, PWM, event counter Prescaler down to 1 second ( crystal = 32 KHz ) 1/1000 sec 12 bit binary coded decimal counter with hard or software start/stop function LCD 20 Segments, 3 or 4 times multiplexed 3 wire serial port , 8 bit, master and slave mode 5 external interrupts (port A, serial interface) 8 internal interrupts (3x prescaler, BCD counter 2x10-bit counter, melody timer, serial interface) timer watchdog and oscillation supervisor Figure 1. Architecture
· · · · · · · · · · · · · · · · ·
Figure 2. Pin Configuration, TQFP52 10 * 10 * 1 mm
Description
The EM6621 is an advanced single chip low cost CMOS 4-bit microcontroller. It contains ROM, RAM, LCD driver, power on reset, watchdog timer, oscillation detection circuit, 10-bit up/down and event counter, 1ms BCD counter, prescaler, voltage level detector (Vld), serial interface and several clock functions. The low voltage feature and low power consumption make it the most suitable controller for battery, stand alone and mobile equipment. The EM6621 is manufactured using EM Microelectronic's advanced low power (ALP) CMOS process.
Typical
· · · · · · · · ·
Applications
Timing device Automotive controls with display Intelligent display driver Measurement equipment Domestic appliance Interactive system with display Timer / sports timing devices Bicycle computers Safety and security devices
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Copyright 2002, EM Microelectronic-Marin SA
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EM6621
EM6621 at a glance
· Power Supply
- Low voltage low power architecture including internal voltage regulator - 1.2 ... 3.6 V battery voltage - 2.6 µA in active mode (Xtal, LCD on, 25 °C) - 0.5 µA in standby mode (Xtal, LCD off, 25 °C) - 0.1 µA in sleep mode (25 °C) - 32 KHz Oscillator
· 4-Bit Input Port A
- Direct input read on the port terminals - Debouncer function available on all inputs - Interrupt request on positive or negative edge - Pull-up or pull-down or none selectable by register - Test variables (software) for conditional jumps - PA[0] and PA[3] are inputs for the event counter - PA[3] is Start/Stop input for the millisecond counter - Reset with input combination (register selectable)
· RAM
- 64 x 4 bit, direct addressable - 64 x 4 bit, indexed addressable
· 4-Bit Bi-directional Port B
- All different functions bit-wise selectable - Direct input read on the port terminals - Data output latches - CMOS or Nch. open drain outputs - Pull-down or pull-up selectable - Weak pull-up in Nch. open drain mode - Selectable PWM, 32kHz, 1kHz and 1Hz output
· ROM
- 4k x 16 bit, metal mask programmable
· CPU
- 4-bit RISC architecture - 2 clock cycles per instruction - 72 basic instructions
· Melody Generator
- Dedicated Buzzer terminal - 7 tones plus silence output - The output can be put tristate (default) - Internal 4-bit timer, usable also in standalone mode - 4 different timer input clocks - Timer with automatic reload or single run - Timer interrupt request when reaching 0
· Main Operating Modes and Resets
- Active mode (CPU is running) - Standby mode (CPU in halt) - Sleep mode (no clock, reset state) - Initial reset on power on (POR) - Watchdog reset (logic and oscillation watchdogs) - Reset terminal - Reset with input combination on port A (register selectable)
· Voltage Level Detector (SVLD)
- 8 different levels from 1.2 V to 4.0 V. - Busy flag during measure
· Prescaler
- 15 stage system clock divider down to 1Hz - 3 Interrupt requests; 1Hz, 32Hz or 8Hz, Blink - Prescaler reset (4kHz to 1Hz)
· 10-Bit Universal Counter
- 10, 8, 6 or 4 bit up/down counting - Parallel load - Event counting (PA[0] or PA[3]) - 8 different input clocks- Full 10 bit or limited (8, 6, 4 bit) compare function - 2 interrupt requests (on compare and on 0) - Hi-frequency input on PA[3] and PA[0] - Pulse width modulation (PWM) output
· Liquid Crystal Display Driver (LCD)
- 20 Segments 3 or 4 times multiplexed - Internal or external voltage multiplier - Free Segment allocation architecture (metal 2 mask) - LCD switch off for power save
· 8-Bit Serial Interface
- 3 wire (Clock, DataIn , DataOut) master/slave mode - READY output during data transfer - Maximum shift clock is equal to the main system clock - Interrupt request to the CPU after 8 bits data transfer - Supports different serial formats - Can be configured as a parallel 4 bit input/output port - Direct input read on the port terminals - All outputs can be put tristate (default) - Selectable pull-downs in input mode - CMOS or Nch. open drain outputs - Weak pull-up selectable in Nch. open drain mode
· Millisecond Counter
- 3 digits binary coded decimal counter (12 bits) - PA[3] input signal pulse width and period measurement - Internal 1000 Hz clock generation - Hardware or software controlled start stop mode - Interrupt request on either 1/10 Sec or 1Sec
· Interrupt Controller
- 5 external and 8 internal interrupt request sources - Each interrupt request can individually be masked - Each interrupt flag can individually be reset - Automatic reset of each interrupt request after read - General interrupt request to CPU can be disabled - Automatic enabling of general interrupt request flag when going into HALT mode.
03/02 REV. D/444
Copyright 2002, EM Microelectronic-Marin SA
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EM6621
Table of Contents
FEATURES _________________________________ 1 DESCRIPTION _______________________________ 1 TYPICAL APPLICATIONS ______________________ 1 EM6621 AT A GLANCE ________________________ 2 1. PIN DESCRIPTION FOR EM6621 ____________ 4 2. OPERATING MODES______________________ 6 2.1 ACTIVE MODE _________________________ 6 2.2 STANDBY MODE________________________ 6 2.3 SLEEP MODE __________________________ 6 3. POWER SUPPLY _________________________ 7 4. RESET _________________________________ 8 4.1 OSCILLATION DETECTION CIRCUIT ___________ 9 4.2 RESET TERMINAL _______________________ 9 4.3 INPUT PORT A RESET FUNCTION ____________ 9 4.4 DIGITAL WATCHDOG TIMER RESET _________ 10 4.5 CPU STATE AFTER RESET _______________ 10 5. OSCILLATOR AND PRESCALER ___________ 11 5.1 OSCILLATOR _________________________ 11 5.2 PRESCALER __________________________ 11 6. INPUT AND OUTPUT PORTS ______________ 13 6.1 PORTS OVERVIEW _____________________ 13 6.2 PORT A_____________________________ 14 6.2.1 IRQ on Port A ___________________ 14 6.2.2 Pull-up or Pull-down ______________ 15 6.2.3 Software Test Variables ___________ 15 6.2.4 Port A for 10-Bit Counter and MSC ___ 15 6.3 PORT A REGISTERS ____________________ 15 6.4 PORT B_____________________________ 17 6.4.1 Input / Output Mode_______________ 17 6.4.2 Pull-up or Pull-down ______________ 18 6.4.3 CMOS / NCH. Open Drain Output____ 18 6.4.4 PW M and Frequency Output________ 19 6.5 PORT B REGISTERS ____________________ 19 6.6 PORT SERIAL_________________________ 20 6.6.1 4-bit Parallel I/O _________________ 20 6.6.2 Pull-up or Pull-down ______________ 21 6.6.3 Nch. Open Drain Outputs __________ 22 6.6.4 General Functional Description______ 22 6.6.5 Detailed Functional Description _____ 23 6.6.6 Output Modes ___________________ 23 6.6.7 Reset and Sleep on Port SP ________ 24 6.7 SERIAL INTERFACE REGISTERS ____________ 25 7. MELODY, BUZZER ______________________ 27 7.1 4-BIT TIMER _________________________ 27 7.1.1 Single Run Mode_________________ 28 7.1.2 Continuos Run Mode______________ 28 7.2 PROGRAMMING ORDER __________________ 29 7.3 MELODY REGISTERS____________________ 29 8. 10-BIT COUNTER _______________________ 31 8.1 FULL AND LIMITED BIT COUNTING___________ 31 8.2 FREQUENCY SELECT AND UP/DOWN COUNTING 32 8.3 EVENT COUNTING _____________________ 33 8.4 COMPARE FUNCTION ___________________ 33 8.5 PULSE WIDTH MODULATION (PWM) ________ 33 8.5.1 How the PWM Generator works._____ 34 8.5.2 PW M Characteristics______________ 34 8.6 COUNTER SETUP ______________________ 35 8.7 10-BIT COUNTER REGISTERS ______________ 35 9. MILLISECOND COUNTER _________________ 37 9.1 PA[3] INPUT FOR MSC __________________ 37 9.2 IRQ FROM MSC _______________________ 37 9.3 MSC-MODES _________________________ 38 9.4 MODE SELECTION ______________________ 38 9.5 MILLISECOND COUNTER REGISTERS _________ 40 10. INTERRUPT CONTROLLER ______________ 41 10.1 INTERRUPT CONTROL REGISTERS ___________ 42 11. SUPPLY VOLTAGE LEVEL DETECTOR ____ 43 11.1 SVLD REGISTER ______________________ 43 12. STROBE OUTPUT______________________44 12.1 STROBE REGISTER _____________________ 44 13. RAM _________________________________ 45 14. LCD DRIVER __________________________ 46 14.1 LCD CONTROL ________________________ 47 14.2 LCD ADDRESSING _____________________ 47 14.3 FREE SEGMENT ALLOCATION ______________ 48 14.4 LCD REGISTERS_______________________48 15. PERIPHERAL MEMORY MAP ____________ 50 16. OPTION REGISTER MEMORY MAP _______ 54 17. ACTIVE SUPPLY CURRENT TEST ________ 55 18. MASK OPTIONS _______________________ 56 18.1 INPUT / OUTPUT PORTS __________________ 56 18.1.1 Port A Metal Options ______________ 56 18.1.2 Port A Metal Options ______________ 56 18.1.3 Port B Metal Options ______________ 57 18.1.4 Port SP Metal Options _____________ 58 18.1.5 Voltage Regulator Option ___________ 59 18.1.6 Debouncer Frequency Option _______ 59 18.1.7 User defined LCD Segment Allocation 59 19. TEMP. AND VOLTAGE BEHAVIORS _______ 60 19.1 IDD CURRENT (TYPICAL) _________________ 60 19.2 PULL-DOW N RESISTANCE (TYPICAL) _________ 60 19.3 PULL-UP RESISTANCE (TYPICAL)____________61 19.4 OUTPUT CURRENTS (TYPICAL) _____________ 61 20. ELECTRICAL SPECIFICATION ___________ 62 20.1 ABSOLUTE MAXIMUM RATINGS _____________ 62 20.2 HANDLING PROCEDURES _________________ 62 20.3 STANDARD OPERATING CONDITIONS _________ 62 20.4 DC CHARACTERISTICS - POWER SUPPLY _____ 62 20.5 SUPPLY VOLTAGE LEVEL DETECTOR _________ 63 20.6 OSCILLATOR __________________________ 63 20.7 DC CHARACTERISTICS - I/O PINS ___________ 64 20.8 LCD SEG[20:1] OUTPUTS _______________ 65 20.9 LCD COM[4:1] OUTPUTS ________________ 65 20.10 DC OUTPUT COMPONENT ______________ 65 20.11 LCD VOLTAGE MULTIPLIER _____________ 65 21. DIE, PAD LOCATION AND SIZE___________66 22. PACKAGE & ORDERING INFORMATION ___ 67 22.1 ORDERING INFORMATION _________________ 68 22.2 PACKAGE MARKING _____________________ 68 22.3 CUSTOMER MARKING____________________68 23. SPEC UPDATE ________________________ 69
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EM6621
1. Pin Description for EM6621
Chip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 T Q FP 52 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 DIL 64 10 11 12 13 14 15 16 18 19 20 21 22 23 26 27 28 29 30 31 33 34 35 36 37 38 39 42 43 44 Signal Name VL1 VL2 VL3 COM[1] COM[2] COM[3] COM[4] SEG[20] SEG[19] SEG[18] SEG[17] SEG[16] SEG[15] SEG[14] SEG[13] SEG[12] SEG[11] SEG[10] SEG[9] SEG[8] SEG[7] SEG[6] SEG[5] SEG[4] SEG[3] SEG[2] SEG[1] Reset Test Function Voltage multiplier level 1 Voltage multiplier level 2 Voltage multiplier level 3 LCD back plane 1 LCD back plane 2 LCD back plane 3 LCD back plane 4 LCD Segment 20 LCD Segment 19 LCD Segment 18 LCD Segment 17 LCD Segment 16 LCD Segment 15 LCD Segment 14 LCD Segment 13 LCD Segment 12 LCD Segment 11 LCD Segment 10 LCD Segment 9 LCD Segment 8 LCD Segment 7 LCD Segment 6 LCD Segment 5 LCD Segment 4 LCD Segment 3 LCD Segment 2 LCD Segment 1 Input reset terminal, internal pull-down 15 KOhm Input test terminal, internal pull-down 15 KOhm Input/output , open drain serial port : SIN parallel out terminal 0 Output , open drain serial port : Ready/CS parallel out terminal 1 Output , open drain serial port : SOUT parallel out terminal 2 Input/output , open drain serial port : SCLK parallel out terminal 3 Input/output, open drain port B terminal 0 Remarks LCD level 1 input, if external supply selected LCD level 2 input, if external supply selected LCD level 3 input, if external supply selected
Not used if 3 times multiplexed
Main reset For EM tests only, ground 0 ! Except when needed for MFP programming Serial interface data in or parallel data[0] in/out Serial interface Ready CS or parallel data[1] in/out Serial interface data out or parallel data[2] in/out Serial interface clock I/O or parallel data[3] in/out Port B data[0] I/O or Ck[1] output
30
30
45
PSP[0]
31
31
46
PSP[1]
32
32
47
PSP[2]
33
33
49
PSP[3]
34
34
50
PB[0]
© EM Microelectronic-Marin SA, 03/99, Rev. B/
03/02 REV. D/444
Copyright 2002, EM Microelectronic-Marin SA
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EM6621
Chip 35 36 37 38 39 40 41 42 43 T Q FP 52 35 36 37 38 39 40 41 42 43 DIL 64 51 52 53 54 55 58 59 60 61 Signal Name PB[1] PB[2] PB[3] PA[0] PA[1] PA[2] PA[3] Buzzer Strobe Function Input/output, open drain port B terminal 1 Input/output, open drain port B terminal 2 Input/output, open drain port B terminal 3 Input port A terminal 0 Input port A terminal 1 Input port A terminal 2 Input port A terminal 3 Output Buzzer terminal Output Strobe terminal Remarks Port B data[1] I/O or Ck[11] output Port B data[2] I/O or Ck[16] output Port B data[3] I/O or PW M output TestVar 1 Event counter TestVar 2 TestVar 3 Event counter, MSC start/stop control
µP reset state or/and port B write or sleep flag out 44 44 62 Vbat = VDD Positive power supply MFP Connection 45 45 63 Vreg Internal voltage regulator Connect to minimum 100nF, MFP connection 46 46 64 Qin/Osc1 Crystal terminal 1 32 KHz crystal, MFP connection 47 47 2 Qout /Osc2 Crystal terminal 2 32 KHz crystal, MFP connection 48 48 3 VSS Negative power supply ref. terminal, MFP connection 49 49 4 C2B Voltage multiplier Not needed if ext. supply 50 50 5 C2A Voltage multiplier Not needed if ext. supply 51 51 6 C1B Voltage multiplier Not needed if ext. supply 52 52 7 C1A Voltage multiplier Not needed if ext. supply Gray shaded areas : Terminals needed for MFP programming connections (VDD, Vreg, Qin, Qout, Test). Figure 3. Typical Configuration
L C D D is p la y
C1 C1 C1 VL3 C2 C2 C1A C1B C2A C2B P o rt A P o rt B P o rt S P B u zze r S tr o b e
C r ys ta l
Q in O out
A ll C a p a c i to r s 1 0 0 n F
VL1 VL2
C O M [4 :1 ]
S E G [2 0 :1 ]
Reset
EM 6621
V D D (V b a t ) V re g Test C3 VSS C4
03/02 REV. D/444
Copyright 2002, EM Microelectronic-Marin SA
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