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Part: EBD10RD4ABFA-6B
Category:
Memory
-> DRAM
-> DDR SDRAM
-> Modules
Description:
Company: Elpida Memory
Datasheet: Download EBD10RD4ABFA-6B datasheet File size : 56 kB
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Datasheet text preview:
PRELIMINARY DATA SHEET
1GB Registered DDR SDRAM DIMM
EBD10RD4ABFA (128M words × 72 bits, 1 Rank)
Description
The EBD10RD4ABFA is 128M words × 72 bits, 1 rank Double Data Rate (DDR) SDRAM registered module, mounting 18 pieces of 512M bits DDR SDRAM sealed in TSOP package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2-bit prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each TSOP on the module board.
Features
· 184-pin socket type dual in line memory module (DIMM) PCB height: 30.48mm Lead pitch: 1.27mm · 2.5V power supply · Data rate: 333Mbps/266Mbps (max.) · 2.5 V (SSTL_2 compatible) I/O · Double Data Rate architecture; two data transfers per clock cycle · Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver · Data inputs and outputs are synchronized with DQS · 4 internal banks for concurrent operation (Component) · DQS is edge aligned with data for READs; center aligned with data for WRITEs · Differential clock inputs (CK and /CK) · DLL aligns DQ and DQS transitions with CK transitions · Commands entered on each positive CK edge; data referenced to both edges of DQS · Auto precharge option for each burst access · Programmable burst length: 2, 4, 8 · Programmable /CAS latency (CL): 2, 2.5 · Refresh cycles: (8192 refresh cycles /64ms) 7.8µs maximum average periodic refresh interval · 2 variations of refresh Auto refresh Self refresh · 1 piece of PLL clock driver, 2 pieces of register driver and 1 piece of serial EEPROM (2k bits) for Presence Detect (SPD) on PCB.
Document No. E0274E40 (Ver. 4.0) Date Published April 2003 (K) Japan URL: http://www.elpida.com Elpida Memory,Inc. 2002-2003
EBD10RD4ABFA
Ordering Information
Data rate Mbps (max.) 333 266 266 Component JEDEC speed bin*1 (CL-tRCD-tRP) DDR333B (2.5-3-3) DDR266A (2-3-3) DDR266B (2.5-3-3) Contact pad Gold
Part number EBD10RD4ABFA-6B EBD10RD4ABFA-7A EBD10RD4ABFA-7B
Package 184-pin DIMM
Mounted devices EDD5104ABTA-6B EDD5104ABTA-6B, -7A EDD5104ABTA-6B, -7A, -7B
Note: 1. Module /CAS latency = component CL + 1
Pin Configurations
Front side 1 pin 52 pin 53 pin 92 pin
93 pin Back side
144 pin 145 pin 184 pin
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Pin name VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC /RESET VSS DQ8 DQ9 DQS1 VDD NC NC VSS DQ10 DQ11 CKE0 VDD DQ16 DQ17 DQS2 VSS A9
Pin No. 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73
Pin name DQS8 A0 CB2 VSS CB3 BA1 DQ32 VDD DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VDD /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD NC DQ48 DQ49
Pin No. 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119
Pin name VSS DQ4 DQ5 VDD DM0/DQS9 DQ6 DQ7 VSS NC NC NC VDD DQ12 DQ13 DM1/DQS10 VDD DQ14 DQ15 NC VDD NC DQ20 A12 VSS DQ21 A11 DM2/DQS11
Pin No. 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165
Pin name VSS DM8/DQS17 A10 CB6 VDD CB7 VSS DQ36 DQ37 VDD DM4/DQS13 DQ38 DQ39 VSS DQ44 /RAS DQ45 VDD /CS0 NC DM5/DQS14 VSS DQ46 DQ47 NC VDD DQ52
Preliminary Data Sheet E0274E40 (Ver. 4.0)
2
EBD10RD4ABFA
Pin No. 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Pin name DQ18 A7 VDD DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD Pin No. 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Pin name VSS NC NC VDD DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL Pin No. 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 Pin name VDD DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VDD DM3/DQS12 A3 DQ30 VSS DQ31 CB4 CB5 VDD CK0 /CK0 Pin No. 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Pin name DQ53 NC VDD DM6/DQS15 DQ54 DQ55 VDD NC DQ60 DQ61 VSS DM7/DQS16 DQ62 DQ63 VDD SA0 SA1 SA2 VDDSPD
Preliminary Data Sheet E0274E40 (Ver. 4.0)
3
EBD10RD4ABFA
Pin Description
Pin name A0 to A12 BA0, BA1 DQ0 to DQ63 CB0 to CB7 /RAS /CAS /WE /CS0 CKE0 CK0 /CK0 DQS0 to DQS8 DM0 to DM8/DQS9 to DQS17 SCL SDA SA0 to SA2 VDD VDD VDDSPD VREF VSS VDDID /RESET NC Function Address input Row address Column address Data input/output Check bit (Data input/output) Row address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input and output data strobe Input and output data strobe Clock input for serial PD Data input/output for serial PD Serial address input Power for internal circuit Power for DQ circuit Power for serial EEPROM Input reference voltage Ground VDD identification flag Reset pin (forces register inputs low) No connection A0 to A12 A0 to A9, A11, A12
Bank select address
Preliminary Data Sheet E0274E40 (Ver. 4.0)
4
EBD10RD4ABFA
Serial PD Matrix*
Byte No. 0 1 2 3 4 5 6 7 8 9
1
Function described Number of bytes utilized by module manufacturer Total number of bytes in serial PD device Memory type Number of row address Number of column address Number of DIMM ranks Module data width Module data width continuation DDR SDRAM cycle time, CL = X -6B -7A, -7B SDRAM access from clock (tAC) -6B -7A, -7B DIMM configuration type Refresh rate/type Primary SDRAM width Error checking SDRAM width SDRAM device attributes: Minimum clock delay back-to-back column access SDRAM device attributes: Burst length supported SDRAM device attributes: Number of banks on SDRAM device SDRAM device attributes: /CAS latency SDRAM device attributes: /CS latency SDRAM device attributes: /WE latency SDRAM module attributes SDRAM device attributes: General
Bit7 1 0 0 0 0 0 0 0
Bit6 0 0 0 0 0 0 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1
Bit5 Bit4 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1
Bit3 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0
Bit2 0 0 1 1 1 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 0 1 0 0 1 0 0 0 0
Bit1 Bit0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0
Hex value 80H 08H 07H 0DH 0CH 01H 48H 00H 04H 60H 75H 70H 75H 02H 82H 04H 04H 01H 0EH 04H 0CH 01H 02H 26H C0H 75H A0H 70H 75H 00H 00H 48H 50H
Comments 128 256 byte SDRAM DDR 13 12 1 72 bits 0 (+) SSTL 2.5V CL = 2.5*3
Voltage interface level of this assembly 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1
10
0.70ns*3 0.75ns*3 ECC 7.8 µs Self refresh ×4 ×4 1 CLK 2, 4, 8 4 2/2.5 0 1 Registered ± 0.2V CL = 2*3
11 12 13 14 15 16 17 18 19 20 21 22 23
Minimum clock cycle time at CLX - 0.5 0 -6B, -7A -7B 1 Maximum data access time (tAC) from clock at CLX - 0.5 0 -6B -7A, -7B 0 0 Minimum clock cycle time at CLX - 1
24
0.70ns*3 0.75ns*3
25 26 27
Maximum data access time (tAC) from 0 clock at CLX - 1 Minimum row precharge time (tRP) 0 -6B -7A, -7B 0
18ns 20ns
Preliminary Data Sheet E0274E40 (Ver. 4.0)
5
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