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Part: EM78P156EHM
Category:
Description: 8-bit Microprocessor With Low-power And High-speed CMOS Technology
Company: ELAN Microelectronics
Datasheet: Download EM78P156EHM datasheet File size : 315 kB
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EM78P156E
I.
GENERAL DESCRIPTION
EM78P156E is an 8-bit microprocessor with low-power and high-speed CMOS technology. There is a 1K*13bit Electrical One Time Programmable Read Only Memory (OTP-ROM) within it. It provides a PROTECTION bit to prevent a user's code from intruding as well as 7 OPTION bits to match the user's requirements. Because of the OTP-ROM, the EM78P156E offers users a convenient way to develop and verify their programs. Moreover, a user's developed code can be programmed easily by an EMC writer.
II.
FEATURES
· · · · Operating voltage range: 2.2V~5.5V Available in temperature range: 0°C~70°C Operating frequency range: DC ~ 36MHz Low power consumption: * less than 1.6 mA at 5V/4MHz * typical of 15 µA at 3V/32KHz * typical of 1 µA during the sleep mode 1Kx13 bits on chip ROM One security register to prevent the code in the OTP memory from intruding One configuration register to match the user's requirements 48x8 bits on chip registers (SRAM) 2 bi-directional I/O ports 5 level stacks for subroutine nesting 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt Two clocks per instruction cycle Power-down mode (SLEEP mode) Three available interruptions * TCC overflow interrupt * Input-port status changed interrupt (wake up from the sleep mode) * External interrupt Programmable free running watchdog timer 8 pull-high pins 7 pull-down pins 8 open-drain pins Two R-option pins Package type: SOP, SOIC and DIP 99.9% single instruction cycle commands
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* This specification is subject to be changed without notice.
B3-1
8.11.1999
EM78P156E
III. PIN ASSIGNMENTS
EM78P156E
P52 P53 TCC RESET VSS P60,INT P61 P62 P63 1 2 3 4 5 6 7 8 9 DIP SOP SOIC 18 17 16 15 14 13 12 11 10 P51 P50 OSCI OSCO VDD P67 P66 P65 P64
Fig. 1 Pin assignments
IV. FUNCTIONAL BLOCK DIAGRAM
OSCI OSCO /RESET TCC
Oscillator/Timing Control WDT Timer
/INT
R2
Prescaler
Stack
ROM
Internal C External R oscillator WDT Time-out
IOCA
R1(TCC)
Interrupt Controller
Instruction register
ALU
RAM
Instruction Decoder
Sleep & Wake Control
R3
R4
ACC
DATA & CONTROL BUS
IOC5 R5
IOC6 R6
P 5 0
P 5 1
P 5 2
P 5 3
PPPPPPPP 66666666 01234567
Fig. 2 Functional block diagram
V.
PIN DESCRIPTION
Symbol I/O I Function * XTAL type : Crystal input terminal or external clock input pin. * ERC type: RC oscillator input pin. * IRC type: 50K ohm pulled high for 4MHz. * XTAL type: Output terminal for crystal oscillator or external clock input pin. * RC type: Instruction clock ouput. * External clock signal input. * Real time clock/counter with Schmitt trigger input pin, must be tied to VDD or VSS if not in use.
Table 1 Pin description-EM78P156E
OSCI
OSCO
I/O
TCC
I
* This specification is subject to be changed without notice.
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EM78P156E
Symbol /RESET P50~P53 P60~P67
I/O I I/O I/O
Function * Input pin with Schmitt trigger. If this pin remains at logic low, the controller will keep in reset condition. * P50~P53 are bi-directional I/O pins. P50 and P51 can also be defined as the R-option pins. P50~P52 can be pulled down by software . * P60~P67 are bi-directional I/O pins. These can be pull-high or can be opendrain by software programming. In addition, P60~P63 can be pull-down also by software. * External interrupt pin triggered by falling edge. * Power supply. * Ground.
/INT VDD VSS
I -
VI. FUNCTION DESCRIPTION
VI.1 Operational Registers 1. R0 (Indirect Addressing Register) · R0 is not a physically implemented register. Its major function is to be an indirect addressing pointer. Any instruction using R0 as a pointer actually accesses data pointed by the RAM Select Register (R4). 2. R1 (Time Clock /Counter) · Increased by an external signal edge which is defined by TE bit (CONT-4) through the TCC pin, or by the instruction cycle clock. · Writable and readable as any other registers. 3. R2 (Program Counter) & Stack · R2 and hardware stacks are 10~12-bit wide. The structure is depicted in Fig. 3. · Generating 1024x13 bits on-chip OTP ROM addresses to the relative programming instruction codes. One program page is 1024 words long. · The contents of R2 are set all "0"s upon a RESET condition. · "JMP" instruction allows the direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC to go to any location within a page. · "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can locate anywhere within a page. " RET" ("RETL K", "RETI") instruction loads the program counter with the contents of the top-level stack. "ADD R2,A" allows a relative address to be added to the current PC, and the ninth and tenth bits of the PC are cleared. · "MOV R2,A" allows to load an address from the "A" register to the lower 8 bits of the PC, and the ninth and tenth bits of the PC are cleared. · Any instruction which would change the contents of R2 (e.g. "ADD R2,A", "MOV R2,A", "BC R2,6",......) will cause the ninth and tenth bits (A8~A9) of the PC to be cleared. Thus, the computed jump is limited to the first 256 locations of a page. · All instructions are single instruction cycle (fclk/2) except the instructions which would change the contents of R2 need one more instruction cycle.
* This specification is subject to be changed without notice.
B3-3
8.11.1999
EM78P156E
CALL
PC
A11 A10
A9 A8
A7 ~ A0
RET RETI RETL
000
00
PAGE 0
3FF
Stack 1 Stack 2 Stack 3 Stack 4 Stack 5
Fig. 3 Program counter organization
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
R0 R1(TCC) R2(PC) R3(Status) R4(RSR) R5(Port5) R6(Port6)
Stack (5 levels)
IOC5 IOC6
RF R10 : : 48x8 Common Register
IOCA IOCB IOCC IOCD IOCE IOCF
: :
3F
R3F
Fig. 4 Data memory configuration
* This specification is subject to be changed without notice.
B3-4
8.11.1999
EM78P156E
4. R3 (Status Register) 7 GP2 · · · · Bit 0 (C) Bit 1 (DC) Bit 2 (Z) Bit 3 (P) 6 GP1 5 GP0 4 T 3 P 2 Z 1 DC 0 C
· Bit 4 (T) · Bit 5~7 (GP0~2) 5.
Carry flag Auxiliary carry flag Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero. Power-down bit. Set to 1 during power-on or by a "WDTC" command and reset to 0 by a "SLEP" command. Time-out bit. Set to 1 by the "SLEP" and "WDTC" commands, or during power-up and reset to 0 by WDT time-out. General-purpose read/write bits.
R4 (RAM Select Register) · Bits 0 ~ 5 are used to select registers (address: 00~06, 0F~3F) in the indirect addressing mode. · Bits 6 ~ 7 are general-purpose read/write bits. · See the configuration of the data memory in Fig.4.
6.
R5 ~ R6 (Port 5 ~ Port 6) · R5 and R6 are I/O registers. · Only the lower 4 bits of R5 are available.
7.
RF (Interrupt Status Register) 7 · · · · · · · · 6 5 4 3 2 EXIF 1 ICIF 0 TCIF
"1" means interrupt request, and "0" means non-interrupt occurence. Bit 0 (TCIF) TCC overflowing interrupt flag. Set when TCC timer overflows, reset by software. Bit 1 (ICIF) Port 6 input status changed interrupt flag. Set when Port 6 input changes, reset by software. Bit 2 (EXIF) External interrupt flag. Set by falling edge on /INT pin, reset by software. Bits 3 ~ 7 Not used. RF can be cleared by instruction but can not be set. IOCF is the interrupt mask register. Note that the result of reading RF is the "logic AND" of RF and IOCF.
8.
R10 ~ R3F · All of these are the 8-bit general-purpose registers.
VI.2 Special Purpose Registers 1. A (Accumulator)
* This specification is subject to be changed without notice.
B3-5
8.11.1999
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