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Part: EM19110
Category:
Multimedia
-> Video
-> A/D Converters
Description: 10-bit 5 MSPS A/D Converter
Company: ELAN Microelectronics
Datasheet: Download EM19110 datasheet File size : 66 kB
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Datasheet text preview:
E 1 1 11 0 EMM99110
10-BIT
1 -BIT 5 A/D CONVERTER 5 0MSPSMSPS A/D CONVERTER
GENERAL DESCRIPTION
EM19110 is a 10-bit, 5 MHZ CMOS A/D converter for high speed and high resolution use. The 2-step parallel structures accompanying with an average technique that external generated reference voltage, the users can tune transfer curve to meet their application.
FEATURES
· · · · · · · · 5 MSPS maximum conversion speed High resolution up to 10 bit Built-in sampling and hold circuit Internal self-bias reference voltage 115 mW low power dissipation at 5MSPS +5V single power supply Available in 24 pin SOP Series EM19110M for 300 mil SOP
APPLICATION
Precision scanner, digital cellular phone and a wide range of fields where high speed and high resolution A/D conversion is required in the digital communication.
PIN ASSIGNMENT
EM19110
OE D0(LSB) D1 D2 D3 D4 D5 D6 D7 D8 D9(MSB) CLK 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 DVSS VRB VRBS AR1 AVSS VIN AVDD VR2 VR3 VRT VRTS DVDD
* This specification are subject to be changed without notice.
5.26.1997
1
EM19110
10-BIT 5 MSPS A/D CONVERTER
FUNCTIONAL BLOCK DIAGRAM
/OE
1 2
Ladder resistors
24
DVSS
D0 D1
23
22
Fine
VRB VRBS
3 4 5
Error
D2 D3
Fine encoder
Comparators with S/ H (6bit)
21
20
VR1
AVSS VIN
AVDD
D4
D5
6 7 8 9
correction
and
Fine encoder
data latches
Fine Comparators with S/ H (6bit)
19 18 17 16
D6
VR2 VR3
D7
Coarse encoder
D8 10 D9 11 CLK 12
Clock center
Coarse Comparators with S/ H (4bit)
15 14
13
VRT
VRTS
DVDD
PIN DESCRIPTIONS
Symbol OE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 CLK DVDD VRTS VRT VR3 VR2 AVDD VIN AVSS VR-1 VRBS VRB DVSS Function Output enable Data output bit 0 (LSB) Data output bit 1 Data output bit 2 Data output bit 3 Data output bit 4 Data output bit 5 Data output bit 6 Data output bit 7 Data output bit 8 Data output bit 9 (MSB) Clock input Digital power supply Top internal reference voltage Top reference voltaget Tap-3 reference voltage Tap-2 reference voltage Analog power supply Analog input voltage Analog ground Tap-1 reference voltage Bottom internal reference voltage Bottom reference voltage Digital ground 5.26.1997
2
* This specification are subject to be changed without notice.
EM19110
10-BIT 5 MSPS A/D CONVERTER
ABSOLUTE MAXIMUM RATINGS (TA=25 °C)
Items Supply voltage Analog input voltage Reference input voltage Operating temperature Sym. V DD VIN VRT,VRB TOPR Rating 7 VSS to VDD VSS to VDD -20 to 65 Unit V V V °C
(FC=5MPS,AVDD=DVDD=5V,VRB=1.0V,V RT=4.0V,Ta=25°C) Parameter Sym. Maximum Conversion Speed FC Supply current IDD Reference pin current I REF Analog input bandwidth BW Analog input capacitance CIN Reference resistance RREF Differential reference voltage VRT-VRB Internal bias reference voltage V RB VRT-VRB Digital input voltage VIH V IL Digital input current IIH IIL Digital output current IOH I OL Digital output current IOZH Output data delay Integral nonlinearity Differential nonlinearity Aperture jitter Sampling delay TDL EL ED taj tds Conditions FC=5MSPS Min. Typ. Max. Unit 5 8 MSPS 23 28 mA 7.5 8.5 9.4 mA 1 MHz 5 pF 320 355 400 1.0 V DD 0.95 1.0 1.05 V 2.9 3.0 3.1 4.0 V 1.0 5 µA 5 -1.1 V 3.7 V 16 V 16 V 20 30 ns ±2.0 LSB ±1.0 LSB 50 ps 4 ns
External bias AVSSVRB VRT AVDD Internal bias short VRB and VRBS Internal bias short VRT and VRTS VDD=max. OE=VSS, VDD=min. OE=VDD VIH=VDD VIL=0V VOH=VDD-0.5V VOL=0.4V VOH=VDD VOL=0V
* This specification are subject to be changed without notice.
5.26.1997
3
EM19110
10-BIT 5 MSPS A/D CONVERTER
TIMING DIAGRAM
Clock
Analog input
N
N+1 N+2 N+3
N+4
Data output
N-3
N-2
N-1
N
N+1
Application Note
1. AVDD ,DVDD ,VSS To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and analog VDD pins, use a ceramic capacitor of about 0.1uF set as close as possible to the pin to bypass to the respective GND's. 2. Signal input Vi Compared with the flash type A/D converter, the input capacitance of the analog input is rather small. However it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability. When driving with an amplifier of low output impedance, parasite oscillation may occur. That may be prevented by inserting a resistance of about 100( in series between the amplifier output and A/D input. 3. Clock input The clock line wiring should be as short as possible also, to avoid any interference with other signals, separate it from other circuits. 4. Reference voltage Voltage between VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and VRB pins to GND, by means of a capacitor about 0.1uF, stable characteristics are obtained. By shorting VRT and VRTS, VRB and VRBS, the self bias function that generates VRT=4.0V and VRB=1.0V, is activated. Also, the users can setup external reference voltage by just connecting VRT and VRB to desired DC voltage under spec. 5. Clock timing * This specification are subject to be changed without notice. 5.26.1997
4
EM19110
10-BIT 5 MSPS A/D CONVERTER
Analog input is sampled with the falling edge of CLK and output as digital data with a delay of 2.5 clocks and with the following rising edge. The delay from the clock rising edge to the data output is the output data delay about 20ns. 6. /OE By connecting /OE to GND output mode is obtained. By connecting to VDD high impedance is obtained. 7. About latch up It is necessary that AVDD and DVDD pins be the common source of power supply. This is to avoid latch up due to the voltage difference between AVDD and DVDD pins when power is ON.
8. Tap reference voltage Tap reference voltage VR1 thru VR3 connect to eighth point along the reference ladder; VR1 is 1/4th up from VRB, VR2 is 2/4th up from VRB, VR3 is 3/4th up from VRB. These pins connecting 0.1uF capacitor to VSS can stabilize the transfer characteristic. By connecting these pins to voltage sources, the piece wise linear transfer curve can be attained.
* This specification are subject to be changed without notice.
5.26.1997
5
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