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Part: M-88L70
Category:
Communication
-> Telephony
-> DTMF (Dual Tone Multiple Frequency)
Description: 3v DTMF Receiver
Company: Clare, Inc.
Datasheet: Download M-88L70 datasheet File size : 875 kB
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Datasheet text preview:
M-88L70
3V DTMF Receiver
Features · Operates between 2.7 and 3.6 volts · Low power consumption · Power-down mode · Inhibit mode · Central office quality and performance · Inexpensive 3.58 MHz time base · Adjustable acquisition and release times · Dial tone suppression · Functionally compatible with Clare's M-8870 Applications · Telephone switch equipment · Mobile radio · Remote control · Paging systems · PCMCIA · Portable TAD · Remote data entry The M-88L70 is a full DTMF Receiver that integrates both bandsplit filter and decoder functions into a single 18-pin DIP or SOIC package. Manufactured using CMOS process technology, the M-88L70 offers low power consumption (18 mW max), precise data handling and 3V operation. Its filter section uses switched capacitor technology for both the high and low group filters and for dial tone rejection. Its decoder uses digital counting techniques to detect and decode all 16 DTMF tone pairs into a 4-bit code. External component count is minimized by provision of an on-chip differential input amplifier, clock generator, and latched tri-state interface bus. Minimal external components required include a low-cost 3.579545 MHz color burst crystal, a timing resistor, and a timing capacitor. Figure 2 Block Diagram Description The M-88L70 monolithic DTMF receiver offers small size, low power consumption and high performance, with 3 volt operation. Its architecture consists of a bandsplit filter section, which separates the high and low group tones, followed by a digital counting section which verifies the frequency and duration of the received tones before passing the corresponding code to the output bus.
Ordering Information Part # M-88L70-01P M-88L70-01S M-88L70-01T Description 18-pin plastic DIP 18-pin SOIC 18-pin SOIC, Tape and Reel
Figure 1 Pin Connections
DS-M88L70-R1
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M-88L70
Filter The low and high group tones are separated by applying the dual-tone signal to the inputs of two 9th order switched capacitor bandpass filters with bandwidths that correspond to the bands enclosing the low and high group tones. The filter also incorporates notches at 350 and 440 Hz, providing excellent dial tone rejection. Each filter output is followed by a single-order switched capacitor section that smoothes the signals prior to limiting. Signal limiting is performed by high-gain comparators provided with hysteresis to prevent detection of unwanted low-level signals and noise. The comparator outputs provide full-rail logic swings at the frequencies of the incoming tones. Decoder The M-88L70 decoder uses a digital counting technique to determine the frequencies of the limited tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm is used to protect against tone simulation by extraneous signals (such as voice) while tolerating small frequency variations. The algorithm ensures an optimum combination of immunity to talkoff and tolerance to interfering signals (third tones) and noise. When the detector recognizes the simultaneous presence of two valid tones (known as "signal condi-
tion"), it raises the Early Steering flag (ESt). Any subsequent loss of signal condition will cause ESt to fall. Steering Circuit Before a decoded tone pair is registered, the receiver checks for a valid signal duration (referred to as "character-recognition-condition"). This check is performed by an external RC time constant driven by ESt. A logic high on ESt causes VC (see Figure 3) to rise as the capacitor discharges. Provided that signal condition is maintained (ESt remains high) for the validation period (tGTP), VC reaches the threshold (VTSt) of the steering logic to register the tone pair, thus latching its corresponding 4-bit code (see Table 2) into the output latch. At this point, the GT output is activated and drives VC to VDD. GT continues to drive high as long as ESt remains high. Finally, after a short delay to allow the output latch to settle, the "delayed steering" output flag (StD) goes high, signaling that a received tone pair has been registered. The contents of the output latch are made available on the 4-bit output bus by raising the threestate control input (OE) to a logic high. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (dropouts) too short to be consid-
Table 1 Pin Functions
Pin 1 2 3 4 5 6 7 8 9 10 11-14 15 16 17 Name IN+ IN GS VREF INH PD OSC1 OSC2 VSS OE Q1, Q2, Q3, Q4 StD ESt St/GT Description Non-inverting input Connections to the front-end differential amplifier -Inverting input Gain select. Gives access to output of front-end amplifier for connection of feedback resistor. Reference voltage output (nominally VDD/2). May be used to bias the inputs at mid-rail. Inhibits detection of tones representing keys A, B, C, and D. This input is internally pulled down. Power down. Logic high powers down the device and inhibits the oscillator. This input is internally pulled down. Clock input 3.579545 MHz crystal connected between these pins completes internal oscillator. Clock output Negative power supply (normally connected to 0 V). Tri-state output enable (input). Logic high enables the outputs Q1 - Q4. Internal pullup. Tri-state outputs. When enabled by OE, provides the code corresponding to the last valid tone pair received (see Table 5.) Delayed steering output. Presents a logic high when a received tone pair has been registered and the output latch is updated. Returns to logic low when the voltage on St/GT falls below VTSt Early steering output. Presents a logic high immediately when the digital algorithm detects a recognizable tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. Steering input/guard time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time constant, and its state is a function of ESt and the voltage on St. (See Figure 5). Positive power supply
18
VDD
2
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M-88L70
ered a valid pause. This capability, together with the ability to select the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements. Guard Time Adjustment Where independent selection of receive and pause are not required, the simple steering circuit of Figure 3 is applicable. Component values are chosen according to the formula: tREC = tDP + tGTP tGTP @ 0.67 RC The value of tDP is a parameter of the device and tREC is the minimum signal duration to be recognized by the receiver. A value for C of 0.1 µF is recommended for most applications, leaving R to be selected by the designer. For example, a suitable value of R for a tREC of 40 ms would be 300 K ohm. A typical circuit using this steering configuration is shown in Figure 4. The timing requirements for most telecommunication applications are satisfied with this circuit. Different steering arrangements may be used to select independently the guard times for tone-present (tGTP) and tone-absent (tGTA). This may be necessary to meet system specifications that place both accept and reject limits on both tone duration and interdigit pause. Guard time adjustment also allows the designer to tailor system parameters such as talkoff and noise immunity. Increasing tREC improves talkoff performance, since it reduces the probability that tones simulated by speech will maintain signal condition long enough to be registered. On the other hand, a relatively short tREC with a long tDO would be appropriate for extremely noisy environments where fast acquisition time and immunity to dropouts would be required. Design information for guard time adjustment is shown in Figure 5. Input Configuration The input arrangement of the M-88L70 provides a differential input operational amplifier as well as a bias source (VREF) to bias the inputs at mid-rail. Provision is made for connection of a feedback resistor to the opamp output (GS) for gain adjustment. In a single-ended configuration, the input pins are connected as shown in Figure 4 with the op-amp connected for unity gain and VREF biasing the input at 1/2VDD. Figure 7 shows the differential configuration, which permits gain adjustment with the feedback resistor R5.
Figure 3 Basic Steering Circuit
Table 2 Tone Decoding
FLOW ANY 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 697 770 852 941 FHIGH ANY 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633 1633 1633 1633 1633 Key (ref.) ANY 1 2 3 4 5 6 7 8 9 0 * # A B C D A B C D OE L H H H H H H H H H H H H H H H H H H H D INH X X X X X X X X X X X X X L L L L H H H H ESt H H H H H H H H H H H H H H H H H L L L L Q4 Q3 Q2 Q1
Z Z Z Z 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 0 0 0 Undetected, the output code will remain the same as the previous detected code.
L = logic low, H = logic high, Z = high impedance, X = don't care
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