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Part: M-8888-01SM
Category:
Communication
-> Telephony
-> Tone Receiver
Description: DTMF Receiver
Company: Clare, Inc.
Datasheet: Download M-8888-01SM datasheet File size : 875 kB
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Datasheet text preview:
M-8888
DTMF Transceiver
Features v CMOS technology · Audmapnticoendand increased noisefor low power cons immunity Complete DTMF transmitter/receiver in a single · chip · Steanntdaalrd 8051, 8086/8 microprocessor port · Cdjusrtaboffice quality and performance guard time · Automatilce tone burst mode A · Call progress mode · Single +5 Volt power supply · 20-pin DIP and SOIC packages · 2 MHz microprocessor port operation · Inexpensive 3.58 MHz crystal · Applications Description The M-8888 is a complete DTMF Transmitter Receiver that features adjustable guard time, automatic tone burst mode, call progress mode, and a fully compatible 8051, 8086/8 microprocessor interface. The receiver portion is based on the industry standard M-8870 DTMF Receiver, while the transmitter uses a switched-capacitor digital-to-analog converter for lowdistortion, highly accurate DTMF signaling. Tone bursts can be transmitted with precise timing by making use of the automatic tone burst mode. To analyze call progress tones, a call progress filter can be selected by an external microprocessor.
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Ordering Information Part # Description
M-8888-01P M-8888-01SM M-8888-01T 20-pin plastic DIP 20-pin plastic SOIC 20-pin plastic SOIC,Tape and Reel
Pin Connections
Block Diagram
DS-M8888-R1
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1
M-8888
Single-Ended Input Configuration Differential Input Configuration
Functional Description M-8888 functions consist of a high-performance DTMF receiver with an internal gain setting amplifier and a DTMF generator that contains a tone burst counter for generating precise tone bursts and pauses. The call progress mode, when selected, allows the detection of call progress tones. A standard 8051, 8086/8 series microprocessor interface allows access to an internal status register, two control registers, and two data registers. Input Configuration The input arrangement consists of a differential input operational amplifier and bias sources (VREF) for biasPin Functions
Name IN+ INGS VREF VSS OSC1 OSC2 TONE WR CS RS0 RD IRQ /CP Description Noninverting op-amp input. Inverting op-amp input. Gain select. Gives access to output of front end differential amplifier for connection of feedback resistor. Reference voltage output. Nominally VDD/2 is used to bias inputs at mid-rail. Negative power supply input. DTMF clock/oscillator input. Clock output. A 3.5795 MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit. Dual tone multifrequency (DTMF) output. Write input. A low on this pin when CS is low enables data transfer from the microprocessor. TTL compatible. Chip select. TTL input (CS = 0 to select the chip). Register select input. See Internal Register Functions on page 7. TTL compatible. Read input. A low on this pin when CS is low enables data transfer to the microprocessor. TTL compatible.. Interrupt request to microprocessor (open-drain output). Also, when call progress (CP) mode has been selected and interrupt enabled, the IRQ/CP pin will output a rectangular wave signal representative of the input signal applied at the input op-amp. The input signal must be within the bandwidth limits of the call progress filter. See Timing Diagrams on page 11. Microprocessor data bus. TTL compatible. Early steering output. Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. Steering input/guard time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St. Positive power supply input.
ing the amplifier inputs at VDD/2. Provisions are made for the connection of a feedback resistor to the op-amp output (GS) for gain adjustment. In a single-ended configuration, the input pins should be connected as shown in the Single-Ended Input Configuration above. Differential Input Configuration above shows the necessary connections for a differential input configuration. Receiver Section The low and high group tones are separated by applying the DTMF signal to the inputs of two sixth-order
D0-D3 ESt St/GT
VDD
2
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Rev. 1
M-8888
switched capacitor bandpass filters with bandwidths that correspond to the low and high group frequencies listed in the Tone Encoding/Decoding below. The low group filter incorporates notches at 350 and 440 Hz, providing excellent dial tone rejection. Each filter output is followed by a single-order switched capacitor filter that smoothes the signals prior to limiting. Limiting is performed by high-gain comparators with hysteresis to prevent detection of unwanted low-level signals. The comparator outputs provide full-rail logic swings at the incoming DTMF signal frequencies. A decoder employs digital counting techniques to determine the frequencies of the incoming tones, and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm protects against tone simulation by extraneous signals (such as voice), while tolerating small deviations in frequency. The algorithm provides an optimum combination of immunity to talkoff with tolerance to interfering frequencies (third tones) and noise. When the detector recognizes the presence of two valid tones (referred to as signal condition), the early steering (ESt) output goes to an active state. Any subsequent loss of signal condition will cause ESt to assume an inactive state. Basic Steering Circuit
by an external RC time constant driven by ESt. A logic high on ESt causes VC (see the Basic Steering Circuit above) to rise as the capacitor discharges. Provided that the signal condition is maintained (ESt remains high) for the validation period (tGTP), VC reaches the threshold (VTSt) of the steering logic to register the tone pair, latching its corresponding 4-bit code (see the Tone Encoding/Decoding on left) into the receive data register. At this point the StGT output is activated and drives VC to VDD. StGT continues to drive high as long as ESt remains high. Finally, after a short delay to allow the output latch to settle, the delayed steering output flag goes high, signaling that a received tone pair has been registered. It is possible to monitor the status of the delayed steering flag by checking the appropriate bit in the status register. If interrupt mode has been selected, the IRQ/CP pin will pull low when the delayed steering flag is active. The contents of the output latch are updated on an active delayed steering transition. This data is presented to the 4-bit bidirectional data bus when the receive data register is read. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (dropout) too short to be considered a valid pause. This capability, together with the ability to select the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements. Guard Time Adjustment: The simple steering circuit shown in the Basic Steering Circuit above is adequate for most applications. Component values are chosen according to the formula: tREC = tDP + tGTP TID = tDA + tGTA 3
Tone Encoding/Decoding
FLOW 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 FHIGH 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633 Digit 1 2 3 4 5 6 7 8 9 0 * # A B C D D3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 D2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 D1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
0 = logic low, 1 = logic high
Steering Circuit: Before a decoded tone pair is registered, the receiver checks for a valid signal duration (referred to as "character recognition condition"). This check is performed
Rev. 1
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