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Part: J108
Category:
Discrete
-> Transistors
-> FETs (Field Effect Transistors)
-> PHEMTs
Description: 25 V, N-channel JFET Switch
Company: Calogic, LLC
Datasheet: Download J108 datasheet File size : 232 kB
Request For quote: Find where to buy J108
Datasheet text preview:
N-Channel JFET Switch
CORPORATION
J108 J110 / SST108 SST110
FEATURES Low Cost Automated Insertion Package Low Insertion Loss No Offset or Error Voltages Generated by Closed Switch Purely Resistive High Isolation Resistance from Driver Fast Switching Low Noise
· · · · · ·
APPLICATIONS Analog Switches Choppers Commutators Low-Noise Audio Amplifiers
· · · ·
PIN CONFIGURATION
SOT-23 G
TO-92
ABSOLUTE MAXIMUM RATINGS (TA = 25oC unless otherwise specified) Gate-Drain or Gate-Source Voltage . . . . . . . . . . . . . . . . -25V Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Storage Temperature Range . . . . . . . . . . . . . -55oC to +150oC Operating Temperature Range . . . . . . . . . . . -55oC to +135oC Lead Temperature (Soldering, 10sec) . . . . . . . . . . . . . +300oC Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360mW Derate above 25oC . . . . . . . . . . . . . . . . . . . . . . . 3.3mW/ oC
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or an y other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D S
G DS
5018
PRODUCT MARKING (SOT-23) SST1 08 I08 SST1 09 I09 SST110 I10
ORDERING INFORMATION Part Package J108-110 Plastic TO-92 XJ108-110 Sorted Chips in Carriers SST109-110 Plastic SOT-23
Temperature Range -55oC to +135oC -55oC to +135oC -55oC to +135oC
ELECTRICAL CHARACTERISTICS (TA = 25oC unless otherwise specified)
SYMBOL IGSS VGS(off) BVGSS IDSS ID(off) rDS(on) Cdg(off) Csg(off) Cdg(on) + Csg(on) td(on) tr td(off) tf PARAMETER Gate Reverse Current (Note 1) Gate -Sou rce Cutoff Voltage Gate -Sou rce Breakdown Voltage Drai n Saturation Current (Note 2) Drain Cutoff Current (Note 1) Drai n-So urce ON Resistance Drain-Gate OFF Capacitance Sou rce-Gate OFF Capacitance Drain-Gate Plus Source-Gate ON Capacitance Turn On Delay Time Rise Time Turn OFF Delay Time Fa ll Time
o
108 109 110 UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAX -3 -3 -3 nA -3 -10 -2 -6 -0.5 -4 V -25 -25 -25 80 40 10 mA 3 3 3 nA 8 12 18 15 15 15 15 85 4 1 6 30 4 1 6 30 15 85 4 1 6 30 15 85 pF
TEST CONDITIONS VDS = 0V, VGS = -15V VDS = 5V, ID = 1µA VDS = 0V, IG = -1µA VDS = 15V, VGS = 0V VDS = 5V, VGS = -10V VDS 0.1V, VGS = 0V VDS = 0, VGS = -10V (Not e 3) f = 1MHz VDS = VGS = 0 (Not e 3) Switching Time Test Conditions (Note 3) J107 J109 J110 VDD 1.5V 1.5V 1.5V VGS(off) -12V -7V -5V RL 150 150 150
ns
NOTES: 1. App roxima tely doubles for every 10 C increase in TA. 2. Pulse test duration = 300µs; duty cycle 3%. 3. Fo r design reference only, not 100% tested.
Others parts begin by j1
J1-1
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