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Part: DBS908
Category:
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Description:
Company: Analogic Corporation
Datasheet: Download DBS908 datasheet File size : 1040 kB
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DBS 908 DBS 908LM
2 GS/s VXI Waveform Digitizer Mezzanine Module
For the Analogic DBS 9905 "C" Size VXI Carrier Module
Introduction
The high-performance DBS 908 Waveform Digitizer is a modular mezzanine board designed for use with the DBS 9905 "C" size VXI carrier module. It features a maximum sampling rate of 2 GigaSamples/second, 8-bit resolution and a 4 MegaSample on-board memory. The DBS 908's compact size and mezzanine board concept permits the use of two modules on the single-slot, "C" size DBS 9905 carrier card. The use of two instruments in a single slot efficiently maximizes your VXI resources while, at the same time, decreasing the cost per slot. The DSB 908 provides a unique combination of speed, resolution and size that maintains the Analogic tradition of implementing innovative ideas that provide state-of-the-art performance at competitive prices. The DBS 908's broad sampling rate range of 100 S/s to 2 GS/s, input bandwidth of DC to 500 MHz (3 dB), 8-bit resolution and 4 MS (16 MS for DBS 908LM) on-board memory position it for use in such applications as Telecommunications, Magnetic Media, Automotive, Time-of-Flight Mass Spectroscopy, Computing, Particle Physics, Military, Explosive-Weapons and Ballistic Testing. The user-programmable front-end further optimizes the digitizer's performance for a variety of applications.
General Description
The DBS 908 features an oscilloscope-type front-end that can be programmed for AC or DC coupling and 50 or 1 M input impedance, therefore making it e a s i l y adaptable for use with either coaxial transmission cable or high impedance probes. The high impedance mode also features very low, 10 pF capacitance that helps minimize the loading effect that can occur when probing high-frequency circuits. A programmable gain amplifier is used to optimize the DBS 908's dynamic range by scaling the input to a Full Scale Range (FSR) that is appropriate for the signal of interest. Available ranges are: 50 mV, 100 mV, 200 mV, 500 mV, 1V, 2V and 5V. A variable offset of ±2V for all mV ranges or ±20V for the higher FSR's also can be employed to maintain the digitizer's dynamic range in instances when the signal of interest is not centered around 0V. The front-end employs calibration circuitry to compensate for any internal offset or gain errors. Calibration is implemented, at the user's discretion, by calling a software function. A crystal-controlled time base that is accurate to ±25 ppm clocks the DBS 908's ADC subsystem. The module's sampling rate is programmable and has a range of 100 S/s to 2 GS/s in increments of 1, 2, 2.5, 4 or 5. A front panel external clock input is provided for divergent sampling rates or to synchronize the ADC clock with the signal of interest. Signal acquisition can be triggered on the signal of interest (internal trigger), an external trigger input, or VXI TTLTRG lines. Whether the trigger source is internal or external, the trigger condition can
Features
2 GS/s Sampling Rate 500 MHz Bandwidth 4 MS Acquisition Memory (16 MS Option) Internal Calibration Input Protection Pre- and Post-Triggering High-Resolution Trigger Timer Interpolator Low Power Consumption (<15W) VXI Plug & Play software
Applications
Telecommunications Magnetic Media Ultrasonic ATE Vibration Analysis Time-of-Flight Mass Spectroscopy Beam Instrumentation
b
us
Signal Input
Input Signal Amplifier 1 M
8 Bit 2 GS/s SH + ADC
8 Bit 2 GS/s
Ext. Memories DEMUX 128K Acq Mem
50
Clk TIMEBASE 4 Meg
Trigger Input
Trigger Signal Amplifier Thr DAC
TRIGGER Circuit
50
1 M Cal DAC
Card Controller
DBS 9905 Interface
VXI Bus
Figure 1. DBS 908 Block Diagram.
be further defined by selecting the trigger slope and level. DC or AC LFReject trigger coupling mode is also provided. Regardless of the trigger source, data is acquired in relation to the specified trigger event and stored as user-defined pre- or post-trigger data. Pre-trigger delay, the storage of data in memory before the desired trigger event, can be adjusted in size from 100% to 0% of acquisition memory. All data samples can be stored before the trigger, immediately after the trigger, or anywhere in between up to the full 4 MS (16 MS for DBS 908LM) of memory. Post-trigger delay, the storage of data in memory exclusively after the trigger event can be adjusted from 0 to 200 MS. In post-trigger mode, acquisition size is not limited to the size of memory available on the DBS 908, since a 28-bit (228) register is used to set the desired number of samples. Trigger hold off is also provided with a range of 1 million events maximum at a resolution of one event or 100 ms maximum at a resolution of 500 ns. Regardless of the trigger mode, the amount of data acquired and stored in onboard memory is programmable and can range from 100 samples to the full 4 MS (16 MS for DBS 908LM). Memory can be configured as a linear buffer or divided into 8K segments for multi-trigger acquisition. The DBS 908 also features a Trigger Time Interpolator (TTI), which can be used in applications that demand precise measurement of the trigger point with respect to the first data point or any trigger to trigger occurrence. The TTI has a resolution of 5 ps max. and is used, by default and dependent on acquisition mode, to time stamp each trigger and the first data point. The user is offered the option of using this timing information to determine when these events occur relative to other events. The VXI Plug & Play compliant software driver supports all functions of the DBS 908 and provides automatic recognition and configuration for all plug-in modules that are in-
stalled in the DBS 9905 carrier unit. Source code is included as well as .DLL files to allow easy porting to most popular programming environments. These drivers exceed VXI Plug & Play requirements to help ensure that system integration and software development time are reduced to an absolute minimum.
MODES OF OPERATION
The DBS 908 has two acquisition modes, Single and Sequence. These modes provide an efficient means of utilizing memory while taking advantage of the DBS 908's high sampling rate.
Single Acquisition Mode
Acquired waveforms are the result of a series of ADC measurements (sample points) taken at a uniform clock rate. In this mode the user selects the desired sampling rate and acquisition memory size and sets the number of segments to 1. Each waveform is trhen recorded with a single trigger.
Sequence Acquisition Mode
In this mode the acquisition memory is divided into a preselected number of segments between 2 and 8000. Each segment is then used to store waveforms acquired from successive triggers. In this mode the trigger re-arm time is less than 500 ns, resulting in very low "dead time", when the digitizer cannot acquire data from a new trigger event. Another feature in this mode is the time stamping of each trigger event using the Trigger Time Interpolator. The TTI makes it possible to determine the time, with 5 ps resolution, from one trigger to any other trigger in the sequential acquisition.
DBS 908/908LM
Specifications
SIGNAL INPUT
Parameter Bandwidth Full Scale Range (p - p) Condition 50 @ 3 dB 1M @ 3 dB Low-level High-level 500 mV FSR 1V FSR Programmable Value DC to 500 MHz DC to 400 MHz 50 mV, 100 mV, 200 mV, 500 mV 1V, 2V, 5V ±2V range ±20V range 1 M/10 pF; 50 ±0.5% 1 single-ended AC or DC 100V (DC+peak AC < 10 kHz) ±5V DC (500 mW) or 5V RMS 15 ns (typ.) Parameter DC Accuracy Integral Linearity ENOB (at 2 GS/s) SFDR Temperature Drift
SYSTEM PERFORMANCE
Condition Value 6.5 > 6.0 44 dB typ. < 1000 ppm FSR/°C < 200 ppm FSR/°C
Offset Range Input Impedance Number of Channels Input Coupling Max. Input Voltage
DC 20 MHz 20 200 MHz 100 MHz Offset Gain
Overload Recovery Time
Overshoot Long Term Settling Time Connector Type
Programmable @1 M Input Impedance) @50 Input Impedance @2% FSR with 2 x FSR positive or negative 100 ns pulse returning to 0V With 500 ps rise time pulse @0.5% of step amplitude (80% FSR)
EXTERNAL INPUTS FOR CLOCK & REFERENCE
Parameter External Clock Frequency External Reference Clock Freq. Clock/Ref. Threshold Clock/Ref Amplitude Connector Type Condition Value 10 MHz to 500 MHz 10 MHz Variable Minimum 3V to +3V 500 mV pk-pk MMCX
< 20% FSR 50 ns (typ.) SMA or BNC Supply Voltage +24 VDC 24 VDC +12 VDC 12 VDC +5 VDC 5.2 VDC 2 VDC Total
DBS 908 POWER REQUIREMENTS
Amps, Max. 0.0 0.0 0.1 0.0 2.5 1.7 0.2 4.5A Watts 0.0 0.0 1.2 0.0 12.5 8.9 0.4 23W
DIGITAL CONVERSION
Parameter Conversion Rate Aperture Uncertainty Acquisition Memory Size Resolution Differential Linearity Condition Internal Clock Value 100 S/s to 2 GS/s ± 1 ps 4 MS (16 MS for DBS 908LM) 8 bits (1:256) ± 0.7 LSB
RELIABILITY TIME BASE
Parameter MTBF Value 25,000 Hrs
Parameter Clock Accuracy Acquisition Modes Trigger Re-arm Time Trigger Time Interpolator
Condition Internal Clock Single Shot Sequence Sequence Mode Sequence Mode
GENERAL
Condition 5% to 90% humidity (non-Condensing) Value 0°C to 40°C
TRIGGER (INTERNAL & EXTERNAL)
Parameter Slope Coupling Trigger Sensitivity Condition Programmable Programmable Internal Trigger External Trigger Internal Trigger Threshold Pre-Trigger Delay Post-Trigger Delay Hold Off Hold Off Resolution Bandwidth Trig. Threshold Max. Input Voltage Impedance Connector Type Value Positive or Negative DC or AC (50 kHz LFReject) From DC to 500 MHz: levels >15% FSR From DC to 500 MHz: levels > 500 mV FSR ± 60% 0% to 100% of data set 0 to 200 MS 1 to 1M events or 500 ns to 100 ms 1 event or 500 ns DC to 500 MHz 3V to +3V ± 5V DC (500 mW) 1 M or 50 BNC or SMA
Specifications subject to change without notice
Programmable
(3 dB) Variable Programmable
Quality Performance
The DBS 908's low noise, low harmonic distortion, step response, flat frequency response and effective number of bits (ENOB) are depicted in the following plots.
FFT analysis of a pure 25 MHz sinewave, measured at 500 mV full scale, showing very low noise floor and little harmonic distortion.
Positive and negative step responses show minimal overshoot and undershoot,
Frequency response is flat and system bandwidth reaching beyond the specified 500 MHz.
Effective bits (top graph) are significantly higher than the minimum guaranteed performance (bottom graph).
Ordering Guide
Model Number DBS 908 DBS 908B DBS 908LM DBS 908LMB Output Connector SMA BNC SMA BNC Memory Size 4 MS 4 MS 16 MS 16 MS
Analogic Corporation Test & Measurement Division 8 Centennial Drive Peabody, MA 01960-7987, USA Tel: (978) 977-3000 Fax: (978) 977-6814 email: t&m_info@analogic.com www.analogic.com
Printed in U.S.A. © 2001 ANALOGIC Corporation Bulletin No. 16-100664 REV 0 7/01
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