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Part: DAC8248F
Category:
Data Conversion
-> DAC (Digital to Analog Converters)
Description:
Company: Analog Devices
Datasheet: Download DAC8248F datasheet File size : 512 kB
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a
Dual 12-Bit (8-Bit Byte) Double-Buffered CMOS D/A Converter DAC8248
PIN CONNECTIONS 24-Pin 0.3" Cerdip (W Suffix), 24-Pin Epoxy DIP (P Suffix), 24-Pin SOL (S Suffix)
FEATURES Two Matched 12-Bit DACs on One Chip 12-Bit Resolution with an 8-Bit Data Bus Direct Interface with 8-Bit Microprocessors Double-Buffered Digital Inputs RESET to Zero Pin 12-Bit Endpoint Linearity ( 1/2 LSB) Over Temperature 5 V to 15 V Single Supply Operation Latch-Up Resistant Improved ESD Resistance Packaged in a Narrow 0.3" 24-Pin DIP and 0.3" 24-Pin SOL Package Available in Die Form APPLICATIONS Multichannel Microprocessor-Controlled Systems Robotics/Process Control/Automation Automatic Test Equipment Programmable Attenuator, Power Supplies, Window Comparators Instrumentation Equipment Battery Operated Equipment GENERAL DESCRIPTION
The DAC8248's double-buffered digital inputs allow both DAC's analog output to be updated simultaneously. This is particularly useful in multiple DAC systems where a common LDAC signal updates all DACs at the same time. A single RESET pin resets both outputs to zero. The DAC8248's monolithic construction offers excellent DACto-DAC matching and tracking over the full operating temperature range. The DAC consists of two thin-film R-2R resistor ladder networks, two 12-bit, two 8-bit, and two 4-bit data registers, and control logic circuitry. Separate reference input and feedback resistors are provided for each DAC. The DAC8248
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The DAC8248 is a dual 12-bit, double-buffered, CMOS digitalto-analog converter. It has an 8-bit wide input data port that interfaces directly with 8-bit microprocessors. It loads a 12-bit word in two bytes using a single control; it can accept either a least significant byte or most significant byte first. For designs with a 12-bit or 16-bit wide data path, choose the DAC8222 or DAC8221.
FUNCTIONAL BLOCK DIAGRAM
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
DAC8248SPECIFICATIONS
ELECTRICAL CHARACTERlSTICS (@ V
Parameter STATIC ACCURACY Resolution Relative Accuracy Differential Nonlinearity Full-Scale Gain Error1 Symbol N INL DNL GFSE
= +5 V or +15 V; VREF A = VREF B = +10 V; VOUTA = VOUT B = 0 V; AGND = DGND = 0 V; TA = Full Temp Range specified in Absolute Maximum Ratings; unless otherwise noted. Specifications apply for DAC A and DAC B.)
DD
Conditions
Min 12
DAC8248 Typ Max
Units Bits LSB LSB LSB LSB LSB LSB p p m /° C nA k %
DAC8248A/E/G DAC8248F/H All Grades are Guaranteed Monotonic DAC8248A/E DAC8248G DAC8248F/H (Notes 2, 3) All Digital Inputs = 0s TA = +25°C TA = Full Temperature Range (Note 4) ±2 ±5 8 11 ± 0.2 VDD = +5 V VDD = +15 V VDD = +5 V VDD = +15 V TA = +25°C TA = Full Temperature Range DB0DB11 WR, LDAC, DAC A/DAC B, LSB/MSB, RESET Digital Inputs = VINL or VINH Digital Inputs = 0 V or VDD VDD = ± 5%
2
± 1/2 ±1 ±1 ±1 ±2 ±4 ±5 ± 10 ± 50 15 ±1
Gain Temperature Coefficient (Gain/Temperature) Output Leakage Current IOUT A (Pin 2), IOUT B (Pin 24) Input Resistance (VREF A, REF B) Input Resistance Match DIGITAL INPUTS Digital Input High Digital Input Low Input Current (VIN = 0 V or VDD and VINL or VINH) Input Capacitance (Note 2) POWER SUPPLY Supply Current DC Power Supply Rejection Ratio (Gain/VDD)
TCGFS ILKG RREF
RREF RREF
VINH VINL IIN C IN
2.4 13.5 0.8 1.5 ± 0.001 ± 1 ± 10 10 15 2 100 0.002
V V V V µA µA pF pF mA µA %/% ns µs pF pF dB dB
IDD PSRR
10
AC PERFORMANCE CHARACTERISTICS Propagation Delay5, 6 tPD Output Current Setting Time6, 7 tS Output Capacitance CO
AC Feedthrough at IOUT A or IOUT B
FTA FTB
TA = +25°C TA = +25°C Digital Inputs = All 0s COUT A, COUT B Digital Inputs = All 1s COUT A, COUT B VREF A to IOUT A; VREF A = 20 V p-p f = 100 kHz; TA = +25°C VREF B to IOUT B; VREF B = 20 V p-p f = 100 kHz; TA = +25°C
350 1 90 120 70 70
2
REV. B
DAC8248
Parameter Switching Characteristics (Notes 2, 8) LSB/MSB Select to Write Set-Up Time LSB/MSB Select to Write Hold Time DAC Select to Write Set-Up Time DAC Select to Write Hold Time LDAC to Write Set-Up Time LDAC to Write Hold Time Data Valid to Write Set-Up Time Data Valid to Write Hold Time Write Pulse Width LDAC Pulse Width Reset Pulse Width t CBS t CBH t AS t AH t LS t LH t DS t DH t WR t LWD t RWD Symbol Conditions VDD = +5 V +25 C 40 C to +85 C (Note 9) 130 0 180 0 120 0 160 0 130 100 80 170 0 210 0 150 0 210 0 150 110 90 DAC8248 VDD = +15 V 55 C to +125 C All Temps (Note 10) 180 0 220 0 160 0 220 0 170 130 90 80 0 80 0 80 0 70 10 90 60 60 ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min Units
NOTES 11 Measured using internal R FB A and RFB B. Both DAC digital inputs = 1111 1111 1111. 12 Guaranteed and not tested. 13 Gain TC is measured from +25°C to TMIN or from +25°C to TMAX. 14 Absolute Temperature Coefficient is approximately +50 ppm/°C. 15 From 50% of digital input to 90% of final analog output current. V REF A = VREF B = +10 V; OUT A, OUT B load = 100 , CEXT = 13 pF. 16 WR, LDAC = 0 V; DB0DB7 = 0 V to V DD or VDD to 0 V. 17 Settling time is measured from 50% of the digital input change to where the output settles within 1/2 LSB of full scale. 18 See Timing Diagram. 19 These limits apply for the commercial and industrial grade products. 10 These limits also apply as typical values for V DD = +12 V with +5 V CMOS logic levels and T A = +25°C. Specifications subject to change without notice.
Burn-In Circuit
REV. B
3
DAC8248
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operates on a single supply from +5 V to +15 V, and it dissipates less than 0.5 mW at +5 V (using zero or VDD logic levels). The device is packaged in a space-saving 0.3", 24-pin DIP. The DAC8248 is manufactured with PMI's highly stable thinfilm resistors on an advanced oxide-isolated, silicon-gate, CMOS technology. PMI's improved latch-up resistant design eliminates the need for external protective Schottky diodes.
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C, unless otherwise noted.)
Package Type 24-Pin Hermetic DIP (W) 24-Pin Plastic DIP (P) 24-Pin SOL (S)
JA1 69 62 72
JC 10 32 24
Units °C/W °C/W °C/W
NOTE 1 JA specified for worst case mounting conditions, i.e., JA is specified for device in socket for cerdip and P-DIP packages; JA is specified for device soldered to printed circuit board for SOL package.
CAUTION
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V AGND to DGND . . . . . . . . . . . . . . . . . . 0.3 V, VDD +0.3 V Digital Input Voltage to DGND . . . . . . . 0.3 V, VDD +0.3 V IOUT A, IOUT B to AGND . . . . . . . . . . . . . . 0.3 V, VDD +0.3 V VREF A, VREF B to AGND . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V VRFB A, VRFB B to AGND . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V Operating Temperature Range AW Version . . . . . . . . . . . . . . . . . . . . . . . 55°C to +125°C EW, FW, FP Versions . . . . . . . . . . . . . . . . 40°C to +85°C GP, HP, HS Versions . . . . . . . . . . . . . . . . . . . 0°C to +70°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C Storage Temperature . . . . . . . . . . . . . . . . . . 65°C to +150°C Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C
1. Do not apply voltages higher than VDD or less than GND potential on any terminal except VREF and RFB. 2. The digital control inputs are Zener-protected; however, permanent damage may occur on unprotected units from high energy electrostatic fields. Keep units in conductive foam at all times until ready to use. 3. Do not insert this device into powered sockets; remove power before insertion or removal. 4. Use proper antistatic handling procedures. 5. Devices can suffer permanent damage and/or reliability degradation if stressed above the limits listed under Absolute Maximum Ratings for extended periods. This is a stress rating only and functional operation at or above this specification is not implied.
ORDERING GUIDE1
Model DAC8248AW2 DAC8248EW DAC8248GP DAC8248FW DAC8248HP DAC8248FP DAC8248HS3
Relative Accuracy (+5 V or +15 V) ± 1/2 LSB ± 1/2 LSB ± 1/2 LSB ± 1 LSB ± 1 LSB ± 1 LSB ± 1 LSB
Gain Error (+5 V or +15 V) ± 1 LSB ± 1 LSB ± 2 LSB ± 4 LSB ± 4 LSB ± 4 LSB ± 4 LSB
Temperature Range 55°C to +125°C 40°C to +85°C 0°C to +70°C 40°C to +85°C 0°C to +70°C 40°C to +85°C 0°C to +70°C
Package Description 24-Pin Cerdip 24-Pin Cerdip 24-Pin Plastic DIP 24-Pin Cerdip 24-Pin Plastic DIP 24-Pin Plastic DIP 24-Pin SOL
NOTES 1 Burn-in is available on commercial and industrial temperature range parts in cerdip, plastic DIP, and TO-can packages. 2 For devices processed in total compliance to MIL-STD-883, add/883 after part number. Consult factory for 883 data sheet. 3 For availability and burn-in information on SO and PLCC packages, contact your local sales office.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the DAC8248 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
4
REV. B
DAC8248
DICE CHARACTERISTICS
1 1. 1 2. 13. 14. 1 5. 1 6. 1 7. 1 8. 1 9. 10. 11. 12.
AGND IOUTA RFB A VREF A DGND DB7(MSB) DB6 DB5 DB4 DB3 DB2 NC
13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24.
NC DB1 DB0(LSB) RESET L S B/ M S B DAC A/DAC B LDAC WR V DD VREF B RFB B IOUT B
SUBSTRATE (DIE BACKSIDE) IS INTERNALLY CONNECTED TO VDD.
Die Size 0.124 × 0.132 inch, 16,368 sq. mils (3.15 × 3.55 mm, 10.56 sq. mm)
WAFER TEST LIMITS @ V
Parameter Relative Accuracy Differential Nonlinearity Full-Scale Gain Error1 Output Leakage ( I O U T A , I O U T B) Input Resistance (VREF A, VREF B) VREF A, VREF B Input Resistance Match Digital Input High Digital Input Low Digital Input Current Supply Current DC Supply Rejection (Gain/VDD)
DD
= +5 V or +15 V, VREF A = VREF B = +10 V, VOUT A = VOUT B = 0 V; AGND = DGND = 0 V; TA = 25 C.
Conditions Endpoint Linearity Error All Grades are Guaranteed Monotonic Digital Inputs = 1111 1111 1111 Digital Inputs = 0000 0000 0000 Pads 2 and 24 Pads 4 and 22 DAC8248G Limit ±1 ±1 ±4 ± 50 8/15 ±1 2.4 13.5 0.8 1.5 ±1 2 0.1 0.002 Units LSB max LSB max LSB max nA max k min/k max % max V min V min V max V max µA max mA max mA max %/% max
Symbol INL DNL G FSE ILKG R REF R REF R REF V INH V INL IIN IDD PSR
VDD = +5 V VDD = +15 V VDD = +5 V VDD = +15 V VIN = 0 V or VDD; VINL or VINH All Digital Inputs VINL or VINH All Digital Inputs 0 V or VDD VDD = ± 5%
NOTES 1 Measured using internal R FB A and RFB B. Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
REV. B
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