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Part: ADP3205
Category:
Description: Multi-phase Imvp-iv Core Controller For Mobile Cpus
Company: Analog Devices
Datasheet: Download ADP3205 datasheet File size : 841 kB
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Multiphase IMVP-IV Core Controller for Mobile CPUs ADP3205
FEATURES Pin Programmable 1-, 2-, or 3-Phase Operation Excellent Static and Dynamic Current Sharing Superior Load Transient Response when Used with ADOPTTM Optimal Positioning Technology Noise-Blanking for Speed and Stability Synchronous Rectification Control for Optimized Light Load Efficiency Soft DAC Output Voltage Transition for VID Change Cycle-by-Cycle Current Limiting Latched or Hiccup Current Overload Protection Masked Power Good during Output Voltage Transients Soft Start-Up without Power-On In-Rush Current Surge 2-Level Overvoltage and Reverse-Voltage Protection APPLICATIONS IMVP-IV CPU Core DC-to-DC Converters Programmable Output Power Supplies GENERAL DESCRIPTION
The ADP3205 is a 1-, 2-, or 3-phase hysteretic peak current mode dc-to-dc buck converter controller dedicated to powering a mobile processor's core. The chip optimized low voltage design runs from the 3.3 V system supply. The chip contains a precision 6-bit DAC whose nominal output voltage is set by VID code. The ADP3205 features high speed operation to allow a minimized inductor size that results in the fastest possible change of current to the output. To further minimize the number of output capacitors, the converter features active voltage positioning enhanced with ADOPT optimal compensation to ensure a superior load transient response. The output signals interface with ADP3415 MOSFET drivers, which that are optimized for high speed and high efficiency. The ADP3205 is capable of providing synchronous rectification control to extend battery lifetime in light load conditions. The ADP3205 is specified over the extended commercial temperature range of 0°C to 100°C and is available in a 40-lead LFCSP package.
FUNCTIONAL BLOCK DIAGRAM
DRV3 DRVLSD3
39 38
DRV2
37
DRVLSD2
36
DRV1 DRVLSD1
35 34
ADP3205
TSYNC 40 PSI HYSSET CLIM/ZCS CMP HYS/CLIM CONTROL AND CS MUX/ PHASE CONTROL VDACREF CURRENT SENSE HYSTERESIS SET MUX AND VBG CLIM SET
33 CS3
CS2 CS1
CS+ CS
CORE CMP
RAMP REG
DRVCTRL DPSLP VREF BOOTSET DPRSET DPRSLP VID5 VID4 VID3 VID2 VID1 VID0 PWRGD CLKEN TPWRGD DPWRGD BOOT SS 19 SS/LATCH-OFF TIMER PRWGD DELAY VREF VBG PRWGD MASKING COREGD EOFSS ALARM LATCHEN CORE BELOW CMP DAC RES NETWORK CORE ABOVE CMP DACREFFB VREF VBG BOOT REF MUX DACREF DPSHIFT SET DPSHIFT
DAC REF DIVIDER
COREFB
PWRGD LATCH
ALARM CONTROL
MASK
DRVCTRL
DVP CMP OVP LATCH
VOV
SD VCC 22
REV. 0
UVLO CMP BIAS ENABLER ALARM RST
BAND GAP AND REF AMP
VREF VBG RST
RVP LATCH RVP CMP
VRV CLAMP
GND
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
(0 C < TA < 100 C, High (H) = VCC, Low (L) = 0 V, VCC = 3.3 V, SD = H, VCOREFB = VREFFB = VDAC ( VDACREF), VREG = VCS = VVID = 1.25 V, RDACREFFB = 50 , to VCC, RCLAMP = 5.1 k to DACREFFB DRV1 DRV2 DRV3 DRV1 DRV2 = CDRV3 = 10 pF, CSS = 0.047 F, RPWRGD = 3 k VCC, HYSSET, DPSHIFT is open, DPSLP = H, DPRSLP = L, VBOOTSET = 1.0 V, VDPRSET = 1.0 V, unless otherwise noted.) Current sunk by a pin has a positive sign; current sourced by a pin has a negative sign.
Parameter SUPPLY UVLO SHUTDOWN Normal Supply Current UVLO Supply Current Shutdown Supply Current UVLO Threshold Symbol I CC I CC(UVLO) ICCSD V CCH V CCL UVLO Hysteresis2 Shutdown Threshold (SD CMOS Input) CORE FEEDBACK POWER GOOD Core Feedback Threshold Voltage VC C H Y S V SDTH Conditions Min Typ 7 SD = L, 3.0 V VCC 3.6 V SD = H VCC Ramping Up, VSS = 0 V VCC Ramping Down VSS Floating 60 2.95 2.65 50 VCC / 2 Max 11 450 Unit mA µA µA V V mV V
ADP368005RS=PECIRFICATIOCNS1C 2 nF, R = =100 k , = = C
VC O R E F B T H
Power Good Output Voltage (Open-Drain Output) Masking Time CLOCK ENABLER Output Voltage Delay Time (PWRGD to CLKEN) DELAYED POWER GOOD Output Current (Open-Drain Output) POWER GOOD DELAY TIMER Timing Threshold Input Current Input Resistance SOFT START/LATCH-OFF TIMER Charge Current Discharge Current Soft-Start Enable Threshold
VP W R G D tPWRGD, MSK3 V CLKENH V CLKENL tDCLKEN I DPWRGDH I DPWRGDL VTPWRGDTH I TPWRGD RTPWRGD I SS V SSEN
0.7 V < VDAC < 1.708 V VCOREFB Ramping Up VCOREFB Ramping Down VCOREFB Ramping Up VCOREFB Ramping Down VCOREFB = V DAC VCOREFB = 0.8 VDAC VCC = 3.3 V VCC = 3.0 V, ICLKEN = 10 µA VCC = 3.6 V, ICLKEN = +10 µA
1 . 1 2 VD A C 1 . 1 0 V DAC 0 . 8 8 V DAC 0 . 8 6 V DAC 0 . 9 5 VCC 0 80 200 2.5 0 10
1 . 1 4 V DAC 1 . 1 2 V DAC 0 . 9 0 V DAC 0 . 8 8 V DAC VCC 0.8
V V µs V V µs µA mA V µA µA µA
3.0 0.4
VCC = 3.0 V, Off VCC = 3.6 V, On
± 0.1 1.0 1.2 0.1 320 32 +0.7
VTPWRGD = 3 V VTPWRGD = 1.3 V VSS = 0.5 V VSS = 0.5 V VREG = 1.25 V, VRAMP = VCOREFB = 1.27 V VSS Ramping Down VSS Ramping Up2 VRAMP = VCOREFB = 1.27 V VSS Ramping Up 10 µA IVREF 10 µA
200 150 1.70 1.666 2.00 1.700
300
mV mV V V
Soft-Start Termination Threshold FIXED REFERENCE Output Voltage
VS S T E R M
2.25 1.734
V REF
VID PROGRAMMED DAC REFERENCE VID Input Threshold (MOS Inputs) VVID0..5 Output Voltage VD A C Static Tolerance (at a Given VID) VDAC/VDAC Settling Time tDACS4
0.5 See VID Code Table I 1.708 V VDAC 0.860 V 0.844 V VDAC 0.700 V CDACREF = 10 nF 0.700 1.0 8.4 3.5 1.708 +1.0 +8.4
V V % mV µs
2
REV. 0
ADP3205
Parameter DAC REFERENCE FEEDBACK Input Resistance CORE COMPARATOR Input Offset Voltage (RampReg) Input Bias Current Output Voltage (DRV1, DRV2, and DRV3) Propagation Delay Time (RAMPDRV1, RAMPDRV2, RAMPDRV3) Rise and Fall Time (DRV1, DRV2, and DRV3) Noise Blanking Time CURRENT SENSE MULTIPLEXER Trans-Resistance Symbol R DACREFFB V COREOS I R E G , IR A M P V DRV_H V DRV_L tRMPODRV_PD 5 tDRV_R 6 tDRV_F6 tBLNK VREG = 1.25 V VREG = VRAMP = 1.25 V VCC = 3.0 V VCC = 3.6 V TA = 25°C Conditions Min Typ 80 ± 0.5 ±1 2.5 0.8 60 70 8 9 80 140 150 10 0 ± 2.5 3 65 85 2 ±4 Max Unit k mV µA V V ns ns ns ns ns ns M V mV µA ns ns
DRV L-H Transition DRV H-L Transition MUX Switch Is ON MUX Switch Is OFF VCS1 = VCS2 = VCS3 VCS = 1.25 V VCS+ = 1.25 V TA = 25°C
Common-Mode Voltage Range CURRENT LIMIT COMPARATOR Input Offset Voltage Input Bias Current Propagation Delay Time HYSTERESIS SETTING Hysteresis Current
RCS1CS+ RCS2CS+ RCS3CS+ V CSCMR VC L I M O S ICS+, ICS tCLPD 5
5
I RAMP_H I CSP_H
VREG = 1.25 V VCOREFB = VRAMP = 1.23 V IHYSSET = 100 µA IHYSSET = 10 µA VRAMP = 1.27 V IHYSSET = 100 µA IHYSSET = 10 µA
85
100 10 100 10 VDAC
115
µA µA µA µA V
85
115
Hysteresis Reference Voltage CURRENT LIMIT SETTING Limit Setting Current
V HYSSET I CS VRAMP = 1.23 V VREG = VCS = VCOREFB = 1.25 V VCS+ = 1.23 V IHYSSET = 100 µA IHYSSET = 10 µA VCS+ = 1.27 V IHYSSET = 100 µA IHYSSET = 10 µA
268
310 31.5 208 21.5
335
µA µA µA µA
178
225
DEEP SLEEP SHIFT SETTING AND CONTROL DPSHIFT Inner Resistance DPSLP Control Threshold (CMOS Input) DEEPER SLEEP VOLTAGE SETTING AND CONTROL7 Input Current DPRSET Gain (DPRSETDACREF) DPRSLP Control Threshold (CMOS Input)
R DPSHIFT VD P S L P T H
DPSLP = L DPSLP = H
140 10 VCC / 2
M V
I DPRSET ADPR V DPRSLPTH
VDPRSET = 1.0 V
± 0.1 1.09 VCC / 2
µA V/V V
REV. 0
3
ADP3205 SPECIFICATIONS (continued)
Parameter BOOT VOLTAGE SETTING Input Current BOOTSET Gain (BOOTSETDACREF) LOW-SIDE DRIVE CONTROL Output Voltage (CMOS Output) Output Current POWER STATE INDICATOR PSI Control Threshold (MOS Input) SYNCHRONOUS TIMER Timing Threshold Input Current Input Resistance OVER/REVERSE VOLTAGE PROTECTION Overvoltage Threshold Reverse-Voltage Threshold Output Voltage (Open-Drain Output) Output Current Symbol I BOOTSET A BOOT Conditions VBOOTSET = 1.0 V Min Typ ± 0.1 1.09 Max Unit µA V/V
V DRVLSD1,2,3 I DRVLSD1,2,3
DPRSLP = H DPRSLP = L DPRSLP = H, VDRVLSD = 1.5 V DPRSLP = L, VDRVLSD = 1.5 V
0 0.7 VCC 2 0.8 0.30 0.5
0.4 VCC
V V mA mA V
VP S I
0.70
VT S Y N T H I TSYNC RTSYNC
VTSYNC = 1.7 V DRV1 or DRV2 or DRV3 = L VTSYNC = 1.3 V DRV1 or DRV2 or DRV3 = H
1.2 ± 0.1 670
V µA
VCOREFB, OVP VCOREFB, RVP VC L A M P I CLAMP
VCOREFB Rising VCOREFB Falling 0.7 VCC VCOREFB = VDAC,VCLAMP = 1.5 V VCOREFB = 2.2 V, VCLAMP = 0.8 V 1
1.9 0.3 VCC 10 6
V V V µA mA
NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 Guaranteed by design. Not production tested. 3 Two test conditions: 1)PWRGD is OK but forced to fail by applying an out-of-the-CoreGood-window voltage ( VCOREFB, BAD = 1.0 V at VVID = 1.25 V setting) to the COREFB pin right after DPRSLP has been asserted/deasserted. PWRGD should not fail immediately only with the specified blanking delay time. 2) PWRGD is forced to fail (VCOREFB, BAD = 1.0 V at VVID = 1.25 V setting) but gets into the CoreGood-window (V COREFB, GOOD = 1.25 V) right after DPRSLP has been asserted/deasserted. PWRGD should not go high immediately only with the specified blanking delay time. 4 Measured from 50% of VID code transition amplitude to the point where V DACREF settles within ± 1% of its steady state value. 5 40 mV p-p amplitude impulse with 20 mV overdrive. Measured from the input threshold intercept point to 50% of the output voltage swing. 6 Measured between the 30% and 70% points of the output voltage swing. 7 DPRSLP circuit meets the minimum 30 ns DPRSLPVR signal assertion requirement; guaranteed by design. Specifications subject to change without notice.
4
REV. 0
ADP3205
ABSOLUTE MAXIMUM RATINGS*
Input Supply Voltage (VCC) . . . . . . . . . . . . . . . . 0.3 V to +7 V All Other Inputs/Outputs . . . . . . . . . . . . 0.3 V to VCC + 0.3 V Operating Ambient Temperature Range . . . . . . . 0°C to 100°C Junction Temperature Range . . . . . . . . . . . . . . . . 0°C to 150°C Junction-to-Ambient Thermal Resistance . . . . . . . . . . 98°C/W Storage Temperature Range . . . . . . . . . . . . . 65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified all other voltages are referenced to GND.
ORDERING GUIDE
Model ADP3205JCP-Reel
Temperature Package Package Range Description Option 0°C to 100°C LFCSP-40 CP-40
Quantity per Reel 2500
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3205 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. 0
5
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