|
|
Part: S6004
Category:
Others
Description: S3005/s3006 Evaluation Board
Company: AMCC (Applied Micro Circuits Corp)
Datasheet: Download S6004 datasheet File size : 127 kB
Request For quote: Find where to buy S6004
Datasheet text preview:
®
DEVICE SPECIFICATION
HD-SDI DATA RETIMER HD-SDI DATA RETIMER GENERAL DESCRIPTION
S8301 S8301
FEATURES
· · · · · · · HD-SDI Retimer 1.485 Gbps operation Lock detect Port bypass +3.3V Power supply SMPTE 292M Compliant 32 Pin TQFP
APPLICATIONS
· Routers · Distribution Amplifiers · Backplanes
The HD-SDI (High Definition Serial Digital Interface) Retimer Circuit is used in full-speed (1.485 Gb/s) HDTV bit stream switching and distribution systems. It contains a monolithic Clock Recovery Unit (CRU), a lock detect feature and a port bypass circuit. The CRU may be used alone to implement a general purpose repeater needed for applications where a re-timed and buffered signal is required. The Data Retimer performs the function of a port bypass circuit followed by a clock and data retiming Phase Locked Loop (CDR). The CDR re-times incoming serial data, detects whether a valid signal is present and outputs a low jitter serial data stream.
Figure 1. System Block Diagram
Video Router
Serial Data In Coax or Fibre Serial Data In
S8301 Crosspoint Switch S2025
S8301
DR
Serial Data Out Coax or Fibre
S8301
S8301
DR
Serial Data Out
December 8, 1998 / Revision A
1
S8301 OVERVIEW
The Data Retimer performs two functions. The first is to perform the function of a Port Bypass Circuit for nodes in a multi-rate switch or router. The low jitter accumulation of the Port Bypass Path is essential in these systems. The second function is to retime and restore signal quality after transmission and equalization. The low jitter transfer peaking and the high jitter tolerance specifications of the Clock and Data Recovery PLL are essential in these applications. In addition, the Lock detect circuit monitors the incoming signals for run length, transition density and frequency. The output of this circuit is useful for link performance monitoring and detection of channel present.
HD-SDI DATA RETIMER
Timing Jitter
The variation in a position of a signal's transitions occuring at a rate greater than a specified frequency, typically 10 Hz. Variations occuring below this specified frequency are termed wander and are not addressed by this practice. Timing jitter is in band with respect to the PLL bandwidth.
Deterministic Jitter Tolerance
Deterministic Jitter Tolerance is the amount of Deterministic jitter that the clock recovery PLL must tolerate.
Lock Detect
The Data Retimer lock detect circuit monitors the selected input signal to detect the presence of the channel. This is done by monitoring the run length, transition density and frequency content of the incoming data. The frequency monitor circuit checks the difference between the divided down recovered clock and the externally supplied reference clock (REFCLK). If the frequency difference of the recovered clock and the reference clock varies by more than ±240 ppm the part will be declared out of lock. In the out of lock state the PLL will lock to the local reference clock and periodically poll the serial data inputs looking for data with valid frequency content. The lock detect output transitions to a logic 1 when the PLL is locked to data, and transitions to a logic 0 when locked to the reference clock.
JITTER PERFORMANCE
The Data Retimer complies with the minimum jitter tolerance requirements proposed by SMPTE 292M when used with differential inputs and outputs. In addition, the Data Retimer is designed for minimum jitter generation and jitter transfer specifications. This allows the optimum system design for arbitrated loop architectures.
Jitter Tolerance
Input jitter tolerance is defined as the amplitude of frequency dependent, random and deterministic jitter that causes the clock recovery PLL to violate the BER specifications.
Alignment Jitter
The variation in position of a signal's transitions relative to those of a clock extracted from that signal. The bandwidth of the clock extraction process determines the low-frequency limit for alignment jitter. Alignment jitter is out of band with respect to the PLL bandwidth.
Figure 3. LOCKDET Function
DATAP/N or ALTP/N
VALID DATA
LOCKDET
Figure 2. Functional Block Diagram
HDTV Clock and Data Retimer
BPSSP/N DOUTP/N
DQ
DATAP/N ALTP/N SEL
M U X
Phase Detect
Loop Filter Divide by 20
CK
VCO
REFCLK
Freq Detect Run Length Detect
LOCKDET
LOCK2REF
2
December 8, 1998 / Revision A
HD-SDI DATA RETIMER
Table 1. Pin Assignment and Description
Pin Name DOUTP DOUTN DATAP DATAN ALTN ALTP REFCLK Level Diff. LVPECL Diff. LVPECL Diff. LVPECL TTL I/O O Pin # 4 5 1 2 28 29 22 Description
S8301
Serial Output Data. This output has been retimed by the Clock and Data Recovery PLL. Open emitter (14-20 mA bias current needed). Serial Input Data. Differential LVPECL. Alternate Serial Input Data. Differential LVPECL. See Figure 9 if not used. Reference clock for the PLL, nominally at 74.25 MHz, rising edge active. See Figure 10 for reference clock biasing. Loop filter capacitor pins. LPF2 to 27 in series with 2.2µF in series with 27 to LPF2. See Figure 8. Active Low. When active the CDR PLL will be forced to lock to the local reference clock (REFCLK). When disconnected, the data retimer will be put into test mode and the PLL will be bypassed for factory testing. Active High. When active, LOCKDET indicates the CDR PLL is locked to the serial data stream. When inactive, the CDR PLL will lock to the local reference clock indicating a loss of data condition. Port Bypass output. When SEL is High, ALTP/N is selected. When SEL is Low, DATAP/N is selected. Active Low. When active, allows 148.5 MHz reference clock. When inactive, allows 74.25 MHz clock. Used for manufacturing test. Normal chip operation when held Low. Ground pins are physically mounted to the die surface, and are an important part of the thermal path. For best thermal performance, all ground pins should be connected to a ground plane, using multiple vias if possible. +3.3V Power Supply. Analog +3.3V Power Supply for the CRU. Analog Ground for the CRU.
I I I
LPF1 LPF2 LCKREFN
Analog 3 State TTL I
12 11 24
LOCKDET
TTL
O
17
BPSSP BPSSN SEL REFSEL TEST GND
Diff. LVPECL TTL TTL 3 Level TTL Ground
O I I I
20 19 30 15 16 6, 18, 23, 31
VCC VCCA GNDA NC Analog Analog
7, 21, 25, 26 3, 8, 14 9, 13
10, 27, 32 No connect.
December 8, 1998 / Revision A
3
Others parts begin by s6
S6-1 S6-2
|
|
|
