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Part: S4801
Category:
Description: STS-48c Pos/atm Sonet Mapper
Company: AMCC (Applied Micro Circuits Corp)
Datasheet: Download S4801 datasheet File size : 79 kB
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S4801
Amazon Device Specification
Revision NC
July 21, 2000
AMCC
Part Number S4801 Revision NC - September 2000
AMAZON
STS-48c POS/ATM SONET MAPPER
Features
· Processes SONET/SDH STS-48c/(STM-16/AU-416c) data streams with full duplex mapping of ATM cells or packets (PPP or LAPS) into SONET/SDH payloads. · Terminates and generates SONET/SDH section, line, and path layers, with transport/section E1, E2, F1 and DCC overhead serial interfaces in both transmit and receive directions. · Provides a 16-bit parallel line-side interface operating at 155 MHz, and a 64/32-bit parallel system-side interface, operating at 50/100 MHz. · Selectable scrambling/descrambling (1+X6+X7) of SONET/SDH frame. · Selectable self-synchronous scramblers (before or after the ATM/HDLC processors) implementing (X43 +1) polynomial for ATM or Packet over SONET applications. · Generic 8-bit microprocessor interface for configuration, control, and status monitoring. · Provides an 8-bit General Purpose I/O (GPIO) register and associated hardware interface pins. · Provides an IEEE 1149.1 JTAG (Boundary Scan ) test port. · Packaged in a 360 CBGA · Implemented in .35 micron, 3.3V process technology.
DEVICE SPECIFICATION
General Description
The S4801 is a highly-integrated VLSI device that provides full-duplex mapping of PPP/LAPS encapsulated packets or ATM cells into SONET/SDH payloads. The S4801 provides full section, line, and path overhead processing and supports framing, scrambling/descrambling, alarm signal insertion/detection, and bit interleaved parity (B1/B2/B3) processing. The S4801 is standards compliant with Bellcore GR-253, ITU G.707, ANSI T1.105 -1995, IETF RFCs 1619/1661/1662/2615 (PPP) and ITU-T COM 7-224-E/D307 (LAPS recommendation) protocols. A general purpose 8-bit microprocessor interface is provided for control, and monitoring. The interface supports both Intel and Motorola type microprocessors, and is capable of operating in either an interrupt driven or polled-mode configurations.
Applications
· · · · · ATM switches Packet over SONET Routers and Switches SONET/SDH Add Drop Multiplexers, Terminal Multiplexers and Digital Cross Connects Test equipment Concentrators
S4801 Block Diagram
TXE1E2F1FRAME RSTB INTB D[7:0] ADDR[11:0] CSN WRB(RWB) RDB(DSB) RDYB(DTACKB) BUSMODE APS_INTB TXSDCCDATA TXSDCCCLK TXLDCCDATA TXLDCCCLK TXE1E2F1DAT
TX8KCLK
TX_ERR TX_EOP TX_VBYTE[2:0] TX FIFO
UTOPIA-3 or FlexBUS-3TM INTERFACE
TX_SYS_DAT[63:0] TX_CLK TX_PRTY TX_ENB TX_SOC/P TX_CLAV/PA RX_CLK_OUT RX_SYS_DAT[63:0] RX_CLK RX_PRTY RX_ENB RX_SOC/P RX_CLAV/PA RX_RVAL RX_VBYTE[2:0] RX_EOP RX_ERR
TX_DATA[15:0] TX_SONETCLK TX_FRAME_IN TX_SONETCLKOUT RX_DATA[15:0] RX_SONETCLK RX_FRAME_IN RX_LOS_IN RX_ALRM_OUT
LINE SIDE INTERFACE
TX FRAMER
TOH INSERT
MICROPROCESSOR I/F TX ATM/HDLC (PPP/LAPS) PROC SCRMBL (X43 + 1)
SPE/VC GENERATE POH MONITOR
SCRMBL (X43 + 1)
RX FRAMER
TOH MONITOR
DE-SCRMBL (X43 + 1) RX ATM/HDLC (PPP/LAPS) CNTRS
RX ATM/HDLC (PPP/LAPS) PROC DE-SCRMBL (X43 + 1) RX FIFO TS_EN
POINTER INTERPRET TOH EXTRACT GPIO/LED REG
JTAG PORT
RXLDCCCLK RXE1E2F1DAT RXE1E2F1FRAME
RXSDCCDATA RXSDCCCLK RXLDCCDATA
GPIO[7:0]
TRSTB
TDO
TDI TCK TMS
AMCC
Device Specification Information - The information contained in this document is about a product in its fully tested and characterized phase. All features described herein are supported. Contact AMCC for updates to this document and the latest product status.
Revision NC - September 2000
S4801 STS-48c POS/ATM SONET Mapper
DEVICE SPECIFICATION
Packet/HDLC Processing
WhenPRELIMINARY PRODUCT DATASHEET configured for POS mode, the S4801's transmit HDLC processor provides the insertion of HDLC framed PPP/LAPS packets into the STS SPE. It will perform packet framing, inter-frame fill and Tx FIFO error recovery. In addition, it optionally performs scrambling (X43+1), either pre or post the HDLC processor, performs transparency processing as required by RFC 1662/ITU-T COM7-D307 and will optionally generate a 16/32 bit FCS. The receive HDLC processor provides for the extraction of PPP/LAPS packets from HDLC frames, transparency removal, de-scrambling (if enabled), FCS error checking, and optionally deletes the HDLC address and control fields.
Overview and Applications
SONET Processing
The S4801 implements SONET/SDH processing and full-duplex ATM/POS mapping functions for STS-48/STM-16 data streams. It supports a single STS-48c/AU-4-16c signal within an STS-48/STM-16. A TOH/SOH interface provides direct add/drop capability for E1, E2, F1, and both Section and Line DCC channels. The S4801 also includes a clear channel mode that enables the direct transmission of system payload from the system interface to the line-side interface. On the transmit side the S4801 generates section, line, and path overhead. It performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, and generates section, line and path Bit Interleaved Parity (B1/B2/B3) for far-end performance monitoring. On the receive side the S4801 processes section, line, and path overhead. It performs framing (A1, A2), descrambling, alarm detection, Pointer Interpretation, Bit Interleaved Parity monitoring (B1/B2/B3), and error count accumulation for performance monitoring.
Line-side Interface
On the line-side, the S4801 supports a 16-bit parallel interface, operating at 155MHz. The device is typically connected to parallel-to-serial / serial-to-parallel converters, which are in turn connected to an electrical-to-optical converter for interfacing to the fiber optic interface. (See figure below.)
ATM Processing
When configured for ATM cell processing, the S4801's transmit ATM processor will perform all necessary cell encapsulation including HEC generation, cell payload scrambling (X43+1) and idle cell insertion to adapt the cell rate to the SPE. When receiving data from the line side, it performs cell delineation, Rx header error correction/detection, descrambling, and detects & deletes idle cells.
System Interface
The S4801 supports a 64/32 bit, 50/100 MHz system interface. When operating in ATM mode, the S4801 supports the 32-bit, 100 MHz, Utopia Level-3 interface, as well as a 64-bit, 50 MHz extension of the Utopia Level-3 specification. When operating in Packet over SONET mode, the S4801 supports a 64/32-bit, 50/100 MHz, FlexBUS-3TM interface.
TYPICAL APPLICATIONS: S4801 in 2.488 Mb/s ATM or POS System
Microprocessor Control Reference Clock 12 Control Addr Data 8 [31:0] [31:0] FlexBUS-3TM System Interface
TX_SONETCLKOUT Fiber Optic SONET Line Side Interface OC-48 Line Interface Ser RxD ± Transceiver CLK Recovery HP / Lucent Sumitomo Ser RxD ± SONET Transmitter 16:1 P/S S3043 S3083 SONET Receiver 1:16 S/P S3044 S3064 TX_SONETCLK TX_DATA[15:0] RX_LOS RX_SONETCLK RX_DATA[15:0]
OR
TX_CLK TX_SYS_DAT[63:0] RX_SYS_DAT[63:0] RX_CLK
IP Router or ATM Switch
IP ROUTER Multi Channel Link Layer Device Switching/ Routing Logic
AMCC S4801
Ser S3040 RxCLK ± S3050
TOH Insertion and Extraction
AMCC 200 Brickstone Square, Andover, MA 01810 Ph: (978) 623-0009 Fax:(978) 623-0024
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