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Part: S4405B-66
Category:
Logic
Description: Bicmos Pecl Clock Generator
Company: AMCC (Applied Micro Circuits Corp)
Datasheet: Download S4405B-66 datasheet File size : 123 kB
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DEVICE SPECIFICATION
12-OUTPUT BiCMOS PLL CLOCK GENERATOR FEATURES
· Generates outputs from 10 MHz to 66 MHz · Four groups of three outputs (12 outputs total) · Eight user-selectable output functions for each group · TTL compatible outputs, with <1.5-ns edge rates · Performs clock doubling, dividing, invert, lead/lag placement · Internal VCO running between 160 to 266 MHz · 1.0µ BiCMOS technology · Output skew less than 500 ps · 52 PQFP package
S4406
GENERAL DESCRIPTION
The S4406 BiCMOS clock generator provides 12 TTL outputs with less than 500 ps of skew. Implemented in AMCC's 1.0µ BiCMOS technology, the internal PLL and divider/delay selector logic allow the user to individually tailor the (4) TTL output groups to the system's needs. The internal VCO can operate between 160 to 266 MHz, and the programmability allows the user to generate output clocks in the 2066 MHz range. The S4406 offers the user the ability to select the appropriate phase and frequency relationship for each of the four groups of three TTL clock outputs. In addition to clock doubling and inversion functions, the S4406 allows any output groups to lead or lag the others by the minimum phase delay of 3.756.25 ns.
APPLICATIONS
· High-performance microprocessor systems · CMOS ASIC systems · Backplane clock deskew and distribution · Compatible with Intel's PentiumTM processor Figure 1. S4406 Block Diagram
REFCLK
PHASE DETECTOR CHARGE PUMP
FBCLK
FILTER
VCO
÷2
I
0
I1
DIVIDE BY 2 OR 4 DELAY GENERATION LOGIC MUX
TSTEN
S
Digital +5V 0V 0 MS2,1,0
3
0 FOUT 0 MODE SELECTION 1 disable 0 FOUT 1 0 FOUT 2 1 FOUT 0
1 MS2,1,0 Analog +5V 0V 2 MS2,1,0
3
MODE SELECTION 2 disable
1 FOUT 1 1 FOUT 2 2 FOUT 0
3
MODE SELECTION 3 disable
2 FOUT 1 2 FOUT 2 3 FOUT 0
3 MS2,1,0
3
MODE SELECTION 4 disable
3 FOUT 1 3 FOUT 2
Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 · (619) 450-9333
Page 1
S4406 FUNCTIONAL DESCRIPTION
The 12 xFOUT02 outputs are the main TTL output clocks that the generator supplies. The mode selection choices are shown in Table 1 and waveform definitions are given in Figure 2. The "x" represents the output group number (14). The frequency of these outputs is determined by the REFCLK clock frequency and the output clock that is tied to the FBCLK input (xFOUT02 can be equal to REFCLK, half of REFCLK, or twice the frequency of REFCLK). Example: In order to meet bus timing specifications for a typical system, designers may need three outputs at 66 MHz for the system clock and processor, a 33-MHz output for the cache controller, and a 33-MHz delayed output for a memory management unit. This system requirement can be met using the S4406 by setting the m o d e select pins for the first group of outputs (0MS2,1,0) to 111, the second group (1MS2,1,0) to Table 1. Mode Selection Options xMS2,1,0 MODE DESCRIPTION
000 001 Disabled. All three outputs at the fundamental output frequency, but early by a minimum phase delay. All three outputs at half the fundamental output frequency and inverted. All three outputs at the fundamental output frequency and inverted. All three outputs at half the fundamental output frequency, but delayed by a minimum phase delay. All three outputs at the fundamental output frequency, but delayed by a minimum phase delay. All three outputs at half the fundamental output frequency. All three outputs at the fundamental output frequency.
FUNCTIONAL DESCRIPTION
110, and the third group (2MS2,1,0) to 101. In this configuration, one of the 33-MHz outputs should be fed back to the FBCLK input. This example makes use of only three of the four output banks, leaving the fourth available for any other clock signals needed. Filter FILTER is the analog signal from the phase detector going into the VCO. This pin is provided so a simple external filter (a single capacitor and resistor) can be included in the phase locked loop of the clock generator. See Figure 3. Phase Delay The minimum phase delay between xFOUT02 signals is a function of the VCO frequency. The VCO frequency can be determined by multiplying the fundamental output frequency by four, or half the fundamental frequency by eight. The minimum phase delay is equal to the period of the VCO frequency: t = 1/(VCO freq). Since the VCO can operate in the 160MHz to 266-MHz range, the range of minimum phase delay values is 6.25 ns to 3.75 ns (See Table 2). Figure 2. Waveform Definitions
Table entry REFCLK Waveform
xFOUT0,1,2
Logical Hi ft
010
I /2
f f/2 f+t ft I
011
I
100
f/2 + t
I/2 t 0 t
101
f+t
Figure 3. External PLL Filter
43 A VCC A +5V .1 µF
110
f/2
S4406
1.5k 42
111
f
FILTER
Note: If f is fed back, the fundamental frequency is equal to REFCLK. If f/2 is fed back, the fundamental frequency is twice REFCLK.
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Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 · (619) 450-9333
BOARD LAYOUT
Test Capabilities TESTEN allows the chip to use the REFCLK input instead of the VCO output to clock the chip. This is used during chip test to allow the counters and control logic to be tested independently of the VCO. In addition, when TESTEN is brought High, an internal RESET pulse is generated. This initializes the internal counter flip-flops to zeros, and at the end of the next clock cycle, the outputs go to a zero state. TESTEN can also be used for board testing to allow the user to control the output clocks from the S4406 by inputting the board clock to the REFCLK input. Table 2. VCO Operating Frequencies xFOUT02
66.6 MHz 50 MHz 40 MHz 33.3 MHz 25 MHz 20 MHz
S4406
tors capable of handling 25 mA. The recommended value for the inductors is in the range from 5 to 100µH, and depends upon the frequency spectrum of the digital power supply noise. Decoupling capacitors are also very important to minimize noise. The decoupling capacitors must have low lead inductance to be effective, so ceramic chip capacitors are recommended. Decoupling capacitors should be located as close to the power pins as physically possible. And the decoupling should be placed on the top surface of the board between the part and its connections to the power and ground planes.
BOARD LAYOUT CONSIDERATIONS
· The S4406 chips are sensitive to noise on the Analog +5 V and Filter pins. Care should be taken during board layout for optimum results. · All decoupling capacitors (C1C4 = 0.1 µF) should be bypassed between VCC and GND, and placed as close to the chip as possible (preferably using ceramic chip caps) and placed on top of board between S4406 and the power and ground plane connections. · No dynamic signal lines should pass through or beneath the filter circuitry area (enclosed by dashed lines in Figure 5) to avoid the possibility of noise due to crosstalk. · The analog VCC supply can be a filtered digital VCC supply as shown below. The ferrite beads or inductors, FB1 and FB2, should be placed within three inches of the chip. · The analog VCC plane should be separated from the digital VCC and ground planes by at least 1/8 inch. Figure 5. Board Layout
VCO FREQ
266 MHz 200 MHz 160 MHz 266 MHz 200 MHz 160 MHz
MIN PHASE DELAY
3.750 ns 5.000 ns 6.250 ns 3.750 ns 5.000 ns 6.250 ns
The bank containing the output used as feedback must be in one of the f/2 modes to ensure the VCO is operating within its 160-266 MHz range. Power Supply Considerations Power for the analog portion of the S4406 chips must be isolated from the digital power supplies to minimize noise on the analog power supply pins. This isolation between the analog and digital power supplies can be accomplished with a simple external power supply filter (Figure 4). The analog power planes are connected to the digital power planes through single ferrite beads (FB1 and FB2) or inducFigure 4. External Power Supply Filter
D GND A GND 45
0.1µF
FB2 D +5V FB1 0.1µF
FB1 ANALOG +5V 0.1 µF
S4406
DIGITAL +5V 10 µF Tantalum (optional) DIGITAL GND
44 43 42 1.5K A +5V
FB2 ANALOG GND
Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 · (619) 450-9333
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