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Part: S2004
Category:
Communication
-> Network
Description: Quad Serial Backplane Device
Company: AMCC (Applied Micro Circuits Corp)
Datasheet: Download S2004 datasheet File size : 209 kB
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Datasheet text preview:
®
DEVICE SPECIFICATION
QUAD SERIAL BACKPLANE DEVICE QUAD SERIAL BACKPLANE DEVICE GENERAL DESCRIPTION
S2004 S2004
FEATURES
· Broad operating rate range (.98 - 1.3 GHz) - 1062 MHz (Fibre Channel) - 1250 MHz (Gigabit Ethernet) line rates - 1/2 Rate Operation · Quad Transmitter with phase-locked loop (PLL) clock synthesis from low speed reference · Quad Receiver PLL provides clock and data recovery · Internally series terminated TTL outputs · On-chip 8B/10B line encoding and decoding for four separate parallel 8-bit channels · 32-bit parallel TTL interface with internal series terminated outputs · Low-jitter serial PECL interface · Individual local loopback control · JTAG 1149.1 Boundary scan on low speed I/O signals · Interfaces with coax, twinax, or fiber optics · Single +3.3V supply, 2.5 W power dissipation · Compact 23mm x 23mm 208 TBGA package
The S2004 facilitates high-speed serial transmission of data in a variety of applications including Gigabit Ethernet, Fibre Channel, serial backplanes, and proprietary point to point links. The chip provides four separate transceivers which can be operated individually or locked together for an aggregate data capacity of >4 Gbps. Each bi-directional channel provides 8B/10B coding/ decoding, parallel to serial and serial to parallel conversion, clock generation/recovery, and framing. The on-chip transmit PLL synthesizes the high-speed clock from a low-speed reference. The on-chip quad receive PLL is used for clock recovery and data retiming on the four independent data inputs. The transmitter and receiver each support differential PECL-compatible I/O for copper or fiber optic component interfaces with excellent signal integrity. Local loopback mode allows for system diagnostics. The chip requires a 3.3V power supply and dissipates 2.5 watts. Figure 1 shows the S2004 and S2204 in a Gigabit Ethernet application. Figure 2 combines the S2004 with a crosspoint switch to demonstrate a serial backplane application. Figure 3 is the input/output diagram. Figures 4 and 5 show the transmit and receive block diagrams, respectively.
APPLICATIONS
· · · · · · Ethernet Backbones Workstation Frame buffer Switched networks Data broadcast environments Proprietary extended backplanes
Figure 1. Typical Quad Gigabit Ethernet Application
GE INTERFACE SERIAL BP DRIVER
MAC
(ASIC)
QUAD GIGABIT ETHERNET INTERFACE
MAC
(ASIC)
TO SERIAL BACKPLANE
S2204 MAC
(ASIC)
S2004
MAC
(ASIC)
July 16, 1999 / Revision C
1
S2004
Figure 2. Typical Backplane Application
MAC
(ASIC)
QUAD SERIAL BACKPLANE DEVICE
MAC
(ASIC)
ATM Fibre Channel Ethernet Etc.
MAC
(ASIC)
MAC
(ASIC)
S2004 MAC
(ASIC)
S2004 MAC
(ASIC)
ATM Fibre Channel Ethernet Etc.
MAC
(ASIC)
MAC
(ASIC)
Crosspoint Switch S2016 S2025 MAC
(ASIC)
MAC
(ASIC)
ATM Fibre Channel Ethernet Etc.
MAC
(ASIC)
MAC
(ASIC)
S2004 MAC
(ASIC)
S2004 MAC
(ASIC)
ATM Fibre Channel Ethernet Etc.
MAC
(ASIC)
BACKPLANE SIGNAL GROUP
MAC
(ASIC)
2
July 16, 1999 / Revision C
QUAD SERIAL BACKPLANE DEVICE
Figure 3. S2004 Input/Output Diagram
TRS TMS TCK TDI TDO
S2004
RESET RATE
REFCLK CLKSEL TMODE
TXAP/N
TCLKO SYNC DINA[0:7] DNA, KGENA TCLKA DINB[0:7] DNB, KGENB TCLKB DINC[0:7] DNC, KGENC TCLKC DIND[0:7] DND, KGEND TCLKD ERRA DOUTA[0:7] EOFA, KFLAGA RCA P/N
TXBP/N
10
TXCP/N
10
10
TXDP/N
10
RXAP/N
10
RXBP/N ERRB DOUTB[0:7] EOFB, KFLAGB RCB P/N RXCP/N ERRC DOUTC[0:7] EOFC, KFLAGC RCC P/N ERRD DOUTD[0:7] EOFD, KFLAGD RCD P/N RXDP/N
10 10
10
CH_LOCK CMODE
LPENA LPENB LPENC LPEND
July 16, 1999 / Revision C
3
Others parts begin by s2
S2-1 S2-2 S2-3 S2-4 S2-5 S2-6 S2-7
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