|
|
Part: S2002
Category:
Communication
-> Network
-> SONET/SDH/ATM/DS3/PHYs/E3 (T3/E3)
-> Backplane
-> Serial Backplane/Crosspoint Switches
Description: Dual Serial Backplane Device
Company: AMCC (Applied Micro Circuits Corp)
Datasheet: Download S2002 datasheet File size : 209 kB
Request For quote: Find where to buy S2002
Datasheet text preview:
®
DEVICE SPECIFICATION
DUAL SERIAL BACKPLANE DEVICE DUAL SERIAL BACKPLANE DEVICE GENERAL DESCRIPTION
S2002 S2002
FEATURES
· Broad operating rate range (.98 - 1.3 GHz) - 1062 MHz (Fibre Channel) - 1250 MHz (Gigabit Ethernet) line rates - 1/2 Rate Operation · Dual Transmitter with phase-locked loop (PLL) clock synthesis from low speed reference · Dual Receiver PLL provides clock and data recovery · Internally series terminated TTL outputs · On-chip 8B/10B line encoding and decoding for two separate parallel 8-bit channels · Dual 8-bit parallel TTL interfaces with internal series terminated outputs · Low-jitter serial PECL interface · Individual local loopback control · JTAG 1149.1 Boundary scan on low speed I/O signals · Interfaces with coax, twinax, or fiber optics · Single +3.3V supply, 1.85 W power dissipation · Compact 21mm x 21mm 156 TBGA package
The S2002 facilitates high-speed serial transmission of data in a variety of applications including Gigabit Ethernet, Fibre Channel, serial backplanes, and proprietary point to point links. The chip provides two separate transceivers which are operated individually for a data capacity of >2 Gbps. Each bi-directional channel provides 8B/10B coding/ decoding, parallel to serial and serial to parallel conversion, clock generation/recovery, and framing. The on-chip transmit PLL synthesizes the high-speed clock from a low-speed reference. The on-chip dual receive PLL is used for clock recovery and data retiming on the two independent data inputs. The transmitter and receiver each support differential PECL-compatible I/O for copper or fiber optic component interfaces with excellent signal integrity. Local loopback mode allows for system diagnostics. The chip requires a 3.3V power supply and dissipates 1.85 watts. Figure 1 shows the S2202 and S2002 in a Gigabit E t h e r n e t application. Figure 2 combines the S2002 with a crosspoint switch to demonstrate a serial backplane application. Figure 3 is the input/ output diagram. Figures 4 and 5 show the transmit and receive block diagrams, respectively.
APPLICATIONS
· · · · · · Ethernet Backbones Workstation Frame buffer Switched networks Data broadcast environments Proprietary extended backplanes
Figure 1. Typical Dual Gigabit Ethernet Application
GE INTERFACE SERIAL BP DRIVER
DUAL GIGABIT ETHERNET INTERFACE
MAC
(ASIC)
TO SERIAL BACKPLANE
S2202 MAC
(ASIC)
S2002
July 16, 1999 / Revision A
1
S2002
Figure 2. Typical Backplane Application
DUAL SERIAL BACKPLANE DEVICE
ATM Fibre Channel Ethernet Etc.
MAC
(ASIC)
MAC
(ASIC)
MAC
(ASIC)
S2002
S2002
MAC
(ASIC)
ATM Fibre Channel Ethernet Etc.
ATM Fibre Channel Ethernet Etc.
MAC
(ASIC)
Crosspoint Switch S2016 S2025
MAC
(ASIC)
MAC
(ASIC)
S2002
S2002
MAC
(ASIC)
ATM Fibre Channel Ethernet Etc.
BACKPLANE SIGNAL GROUP
2
July 16, 1999 / Revision A
DUAL SERIAL BACKPLANE DEVICE
Figure 3. S2002 Input/Output Diagram
TRS TMS TCK TDI TDO
S2002
RESET RATE
REFCLK CLKSEL TMODE TCLKO SYNC DINA[0:7] DNA, KGENA TCLKA DINB[0:7] DNB, KGENB TCLKB ERRA DOUTA[0:7] EOFA, KFLAGA RCA P/N
TXAP/N
TXBP/N
10
10
RXAP/N
10
RXBP/N ERRB DOUTB[0:7] EOFB, KFLAGB RCB P/N
10
TESTMODE TESTMODE1 CMODE
LPENA LPENB
July 16, 1999 / Revision A
3
Others parts begin by s2
S2-1 S2-2 S2-3 S2-4 S2-5 S2-6 S2-7
|
|
|
