|
|
Part: EPM7256AETI144-7
Category:
FPGAs/PLDs
-> FPGA (Field Programmable Gate Array)
Description: Programmable Logic , 256 Macrocells, 16 Logic Array Blocks, 120 I/o Pins, 7ns
Company: Altera Corporation
Datasheet: Download EPM7256AETI144-7 datasheet File size : 2165 kB
Request For quote: Find where to buy EPM7256AETI144-7
Datasheet text preview:
MAX 7000A
®
Includes MAX 7000AE
Programmable Logic Device
Data Sheet
October 2002, ver. 4.3
Features...
High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1) 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability MAX 7000AE device in-system programmability (ISP) circuitry compliant with IEEE Std. 1532 EPM7128A and EPM7256A device ISP circuitry compatible with IEEE Std. 1532 Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1 Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71 Enhanced ISP features Enhanced ISP algorithm for faster programming (excluding EPM7128A and EPM7256A devices) ISP_Done bit to ensure complete programming (excluding EPM7128A and EPM7256A devices) Pull-up resistor on I/O pins during in-system programming Pin-compatible with the popular 5.0-V MAX 7000S devices High-density PLDs ranging from 600 to 10,000 usable gates Extended temperature range
f
For information on in-system programmable 5.0-V MAX 7000 or 2.5-V MAX 7000B devices, see the MAX 7000 Programmable Logic Device Family Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet.
Altera Corporation
DS-M7000A-4.3
1
MAX 7000A Programmable Logic Device Data Sheet
Table 1. MAX 7000A Device Features Feature
Usable gates Macrocells Logic array blocks Maximum user I/O pins tPD (ns) tSU (ns) tFSU (ns) tCO1 (ns) fCNT (MHz)
EPM7032AE
600 32 2 36 4.5 2.9 2.5 3.0 227.3
EPM7064AE
1,250 64 4 68 4.5 2.8 2.5 3.1 222.2
EPM7128AE
2,500 128 8 100 5.0 3.3 2.5 3.4 192.3
EPM7256AE
5,000 256 16 164 5.5 3.9 2.5 3.5 172.4
EPM7512AE
10,000 512 32 212 7.5 5.6 3.0 4.7 116.3
...and More Features
4.5-ns pin-to-pin logic delays with counter frequencies of up to 227.3 MHz MultiVoltTM I/O interface enables device core to run at 3.3 V, while I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), spacesaving FineLine BGATM , and plastic J-lead chip carrier (PLCC) packages Supports hot-socketing in MAX 7000AE devices Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance PCI-compatible Bus-friendly architecture, including programmable slew-rate control Open-drain output option Programmable macrocell registers with individual clear, preset, clock, and clock enable controls Programmable power-up states for macrocell registers in MAX 7000AE devices Programmable power-saving mode for 50% or greater power reduction in each macrocell Configurable expander product-term distribution, allowing up to 32 product terms per macrocell Programmable security bit for protection of proprietary designs 6 to 10 pin- or logic-driven output enable signals Two global clock signals with optional inversion Enhanced interconnect resources for improved routability Fast input setup times provided by a dedicated path from I/O pin to macrocell registers Programmable output slew-rate control Programmable ground pins
2
Altera Corporation
MAX 7000A Programmable Logic Device Data Sheet
Software design support and automatic place-and-route provided by Altera's development systems for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest Programming support with Altera's Master Programming Unit (MPU), MasterBlasterTM serial/universal serial bus (USB) communications cable, ByteBlasterMVTM parallel port download cable, and BitBlasterTM serial download cable, as well as programming hardware from third-party manufacturers and any JamTM STAPL File (.jam), Jam Byte-Code File (.jbc), or Serial Vector Format File- (.svf) capable in-circuit tester
General Description
MAX 7000A (including MAX 7000AE) devices are high-density, highperformance devices based on Altera's second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROMbased MAX 7000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 7000A devices in the -4, -5, -6, -7, and some -10 speed grades are compatible with the timing requirements for 33 MHz operation of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 2. Table 2. MAX 7000A Speed Grades Device -4
EPM7032AE EPM7064AE EPM7128A EPM7128AE EPM7256A EPM7256AE EPM7512AE
Speed Grade -5 -6 -7 v v v v v v v v v v v -1 0 v v v v v v v v v v -12 v v
Altera Corporation
3
MAX 7000A Programmable Logic Device Data Sheet
The MAX 7000A architecture supports 100% transistor-to-transistor logic (TTL) emulation and high-density integration of SSI, MSI, and LSI logic functions. It easily integrates multiple devices including PALs, GALs, and 22V10s devices. MAX 7000A devices are available in a wide range of packages, including PLCC, BGA, FineLine BGA, Ultra FineLine BGA, PQFP, and TQFP packages. See Table 3 and Table 4. Table 3. MAX 7000A Maximum User I/O Pins Device 44-Pin PLCC 44-Pin TQFP Note (1) 49-Pin Ultra FineLine BGA (2)
41 68 68
84-Pin PLCC
100-Pin TQFP
100-Pin FineLine BGA (3)
68 84 84 84
EPM7032AE EPM7064AE EPM7128A EPM7128AE EPM7256A EPM7256AE EPM7512AE
36 36
36 36 68 84 84 84 84
Table 4. MAX 7000A Maximum User I/O Pins Device
EPM7032AE EPM7064AE EPM7128A EPM7128AE EPM7256A EPM7256AE EPM7512AE Notes to tables:
(1) ( 2)
Note (1) 256-Pin BGA 256-Pin FineLine BGA (3)
144-Pin TQFP
169-Pin Ultra 208-Pin PQFP FineLine BGA (2)
100 100 120 120 120 100 164 164 176 212
100 100 164 164 212
(3)
When the IEEE Std. 1149.1 (JTAG) interface is used for in-system programming or boundary-scan testing, four I/O pins become JTAG pins. A ll Ultra FineLine BGA packages are footprint-compatible via the SameFrameTM feature. Therefore, designers can design a board to support a variety of devices, providing a flexible migration path across densities and pin counts. Device migration is fully supported by Altera development tools. See "SameFrame Pin-Outs" on page 15 for more details. A ll FineLine BGA packages are footprint-compatible via the SameFrame feature. Therefore, designers can design a board to support a variety of devices, providing a flexible migration path across densities and pin counts. Device migration is fully supported by Altera development tools. See "SameFrame Pin-Outs" on page 15 for more details.
4
Altera Corporation
MAX 7000A Programmable Logic Device Data Sheet
MAX 7000A devices use CMOS EEPROM cells to implement logic functions. The user-configurable MAX 7000A architecture accommodates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations during design development and debug cycles, and can be programmed and erased up to 100 times. MAX 7000A devices contain from 32 to 512 macrocells that are combined into groups of 16 macrocells, called logic array blocks (LABs). Each macrocell has a programmable-AND/fixed-OR array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. To build complex logic functions, each macrocell can be supplemented with both shareable expander product terms and highspeed parallel expander product terms, providing up to 32 product terms per macrocell. MAX 7000A devices provide programmable speed/power optimization. Speed-critical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power. This speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50% or lower power while adding only a nominal timing delay. MAX 7000A devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non-speed-critical signals are switching. The output drivers of all MAX 7000A devices can be set for 2.5 V or 3.3 V, and all input pins are 2.5-V, 3.3-V, and 5.0-V tolerant, allowing MAX 7000A devices to be used in mixed-voltage systems. MAX 7000A devices are supported by Altera development systems, which are integrated packages that offer schematic, text--including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)--and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry-standard PC- and UNIX-workstation-based EDA tools. The software runs on Windows-based PCs, as well as Sun SPARCstation, and HP 9000 Series 700/800 workstations.
f
For more information on development tools, see the MAX+PLUS II Programmable Logic Development System & Software Data Sheet and the Quartus Programmable Logic Development System & Software Data Sheet.
Altera Corporation
5
Others parts begin by ep
EP-1 EP-2 EP-3 EP-4 EP-5 EP-6 EP-7 EP-8 EP-9 EP-10 EP-11 EP-12 EP-13 EP-14 EP-15 EP-16 EP-17 EP-18 EP-19 EP-20 EP-21 EP-22 EP-23 EP-24 EP-25 EP-26 EP-27 EP-28 EP-29 EP-30 EP-31 EP-32 EP-33 EP-34 EP-35 EP-36 EP-37 EP-38 EP-39 EP-40 EP-41
|
|
|
