|
|
Part: EPM7128B
Category:
FPGAs/PLDs
-> PLDs (Programmable Logic Devices)
Description:
Company: Altera Corporation
Datasheet: Download EPM7128B datasheet File size : 188 kB
Request For quote: Find where to buy EPM7128B
Datasheet text preview:
MAX 7000
®
Programmable Logic Device Family
Data Sheet
December 2002, ver. 6.5
Features...
High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices ISP circuitry compatible with IEEE Std. 1532 Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2) 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect) PCI-compliant devices available
f
For information on in-system programmable 3.3-V MAX 7000A or 2.5-V MAX 7000B devices, see the MAX 7000A Programmable Logic Device Family Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet.
Table 1. MAX 7000 Device Features Feature
Usable gates Macrocells Logic array blocks Maximum user I/O pins tPD (ns) tSU (ns) tFSU (ns) tCO1 (ns) fCNT (MHz)
EPM7032
600 32 2 36 6 5 2.5 4 151.5
EPM7064
1,250 64 4 68 6 5 2.5 4 151.5
EPM7096
1,800 96 6 76 7.5 6 3 4.5 125.0
EPM7128E
2,500 128 8 100 7.5 6 3 4.5 125.0
EPM7160E
3,200 160 10 104 10 7 3 5 100.0
EPM7192E
3,750 192 12 124 12 7 3 6 90.9
EPM7256E
5,000 256 16 164 12 7 3 6 90.9
Altera Corporation
DS-MAX7000-6.5
1
MAX 7000 Programmable Logic Device Family Data Sheet
Table 2. MAX 7000S Device Features Feature
Usable gates Macrocells Logic array blocks Maximum user I/O pins tPD (ns) tSU (ns) tFSU (ns) tCO1 (ns) fCNT (MHz)
EPM7032S
600 32 2 36 5 2.9 2.5 3.2 175.4
EPM7064S
1,250 64 4 68 5 2.9 2.5 3.2 175.4
EPM7128S
2,500 128 8 100 6 3.4 2.5 4 147.1
EPM7160S
3,200 160 10 104 6 3.4 2.5 3.9 149.3
EPM7192S
3,750 192 12 124 7.5 4.1 3 4.7 125.0
EPM7256S
5,000 256 16 164 7.5 3.9 3 4.7 128.2
...and More Features
Open-drain output option in MAX 7000S devices Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls Programmable power-saving mode for a reduction of over 50% in each macrocell Configurable expander product-term distribution, allowing up to 32 product terms per macrocell 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages Programmable security bit for protection of proprietary designs 3.3-V or 5.0-V operation MultiVoltTM I/O interface operation, allowing devices to interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is not available in 44-pin packages) Pin compatible with low-voltage MAX 7000A and MAX 7000B devices Enhanced features available in MAX 7000E and MAX 7000S devices Six pin- or logic-driven output enable signals Two global clock signals with optional inversion Enhanced interconnect resources for improved routability Fast input setup times provided by a dedicated path from I/O pin to macrocell registers Programmable output slew-rate control Software design support and automatic place-and-route provided by Altera's development system for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations
2
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, and VeriBest Programming support Altera's Master Programming Unit (MPU) and programming hardware from third-party manufacturers program all MAX 7000 devices The BitBlasterTM serial download cable, ByteBlasterMVTM parallel port download cable, and MasterBlasterTM serial/universal serial bus (USB) download cable program MAX 7000S devices
General Description
The MAX 7000 family of high-density, high-performance PLDs is based on Altera's second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 3 for available speed grades.
Table 3. MAX 7000 Speed Grades Device -5
EPM7032 EPM7032S EPM7064 EPM7064S EPM7096 EPM7128E EPM7128S EPM7160E EPM7160S EPM7192E EPM7192S EPM7256E EPM7256S
Speed Grade -6 v v v v v v -7 v v v v v v v v v v v v v v -10P -1 0 v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v -12P -12 v -1 5 v -15T v -20
Altera Corporation
3
MAX 7000 Programmable Logic Device Family Data Sheet
The MAX 7000E devices--including the EPM7128E, EPM7160E, EPM7192E, and EPM7256E devices--have several enhanced features: additional global clocking, additional output enable controls, enhanced interconnect resources, fast input registers, and a programmable slew rate. In-system programmable MAX 7000 devices--called MAX 7000S devices--include the EPM7032S, EPM7064S, EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices. MAX 7000S devices have the enhanced features of MAX 7000E devices as well as JTAG BST circuitry in devices with 128 or more macrocells, ISP, and an open-drain output option. See Table 4. Table 4. MAX 7000 Device Features Feature EPM7032 EPM7064 EPM7096 All MAX 7000E Devices All MAX 7000S Devices v v(1) v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v
ISP via JTAG interface JTAG BST circuitry Open-drain output option Fast input registers Six global output enables Two global clocks Slew-rate control MultiVolt interface (2) Programmable register Parallel expanders Shared expanders Power-saving mode Security bit PCI-compliant devices available Notes:
(1 ) (2 )
A vailable only in EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices only. The MultiVolt I/O interface is not available in 44-pin packages.
4
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
The MAX 7000 architecture supports 100% TTL emulation and high-density integration of SSI, MSI, and LSI logic functions. The MAX 7000 architecture easily integrates multiple devices ranging from PALs, GALs, and 22V10s to MACH and pLSI devices. MAX 7000 devices are available in a wide range of packages, including PLCC, PGA, PQFP, RQFP, and TQFP packages. See Table 5. Table 5. MAX 7000 Maximum User I/O Pins Device Note (1) 160Pin PQFP 160Pin PGA 192Pin PGA 208Pin PQFP 208Pin RQFP
4444446884- 100- 100Pin Pin Pin Pin Pin Pin Pin PLCC PQFP TQFP PLCC PLCC PQFP TQFP
36 36 36 36 36 36 36 36 36 52 52 68 68 64 68 68 64 64 76 84 84 84 84 (2) 84 (2) 68 68
EPM7032 EPM7032S EPM7064 EPM7064S EPM7096 EPM7128E EPM7128S EPM7160E EPM7160S EPM7192E EPM7192S EPM7256E EPM7256S Not es:
(1) (2)
100 100 104 104 124 124 132 (2) 164 164 (2) 164 164 124
When the JTAG interface in MAX 7000S devices is used for either boundary-scan testing or for ISP, four I/O pins become JTAG pins. Perform a complete thermal analysis before committing a design to this device package. For more information, see the Operating Requirements for Altera Devices Data Sheet.
MAX 7000 devices use CMOS EEPROM cells to implement logic functions. The user-configurable MAX 7000 architecture accommodates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations during design development and debug cycles, and can be programmed and erased up to 100 times.
Altera Corporation
5
Others parts begin by ep
EP-1 EP-2 EP-3 EP-4 EP-5 EP-6 EP-7 EP-8 EP-9 EP-10 EP-11 EP-12 EP-13 EP-14 EP-15 EP-16 EP-17 EP-18 EP-19 EP-20 EP-21 EP-22 EP-23 EP-24 EP-25 EP-26 EP-27 EP-28 EP-29 EP-30 EP-31 EP-32 EP-33 EP-34 EP-35 EP-36 EP-37 EP-38 EP-39 EP-40 EP-41
|
|
|
