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Part: EPF8452A
Category:
FPGAs/PLDs
-> FPGA (Field Programmable Gate Array)
-> SRAM-based FPGA/PAL
Description: Programmable Logic Device Family (4k Gates)
Company: Altera Corporation
Datasheet: Download EPF8452A datasheet File size : 188 kB
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Datasheet text preview:
FLEX 8000
®
Programmable Logic Device Family
Data Sheet
January 2003, ver. 11.1
1
Features...
Low-cost, high-density, register-rich CMOS programmable logic device (PLD) family (see Table 1) 2,500 to 16,000 usable gates 282 to 1,500 registers System-level features In-circuit reconfigurability (ICR) via external configuration devices or intelligent controller Fully compliant with the peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 5.0-V operation Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 on selected devices MultiVoltTM I/O interface enabling device core to run at 5.0 V, while I/O pins are compatible with 5.0-V and 3.3-V logic levels Low power consumption (typical specification is 0.5 mA or less in standby mode) Flexible interconnect FastTrack® Interconnect continuous routing structure for fast, predictable interconnect delays Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions) Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions) Tri-state emulation that implements internal tri-state nets Powerful I/O pins Programmable output slew-rate control reduces switching noise
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FLEX 8000
Table 1. FLEX 8000 Device Features Feature
Usable gates Flipflops Logic array blocks (LABs) Logic elements (LEs) Maximum user I/O pins
EPF8282A EPF8282AV
2,500 282 26 208 78
EPF8452A
4,000 452 42 336 120
EPF8636A
6,000 636 63 504 136
EPF8820A
8,000 820 84 672 152
EPF81188A EPF81500A
12,000 1,188 126 1,008 184 16,000 1,500 162 1,296 208
Altera Corporation
DS-F8000-11.1
1
FLEX 8000 Programmable Logic Device Family Data Sheet
JTAG BST circuitry
Yes
No
Yes
Yes
No
Yes
...and More Features
Peripheral register for fast setup and clock-to-output delay Fabricated on an advanced SRAM process Available in a variety of packages with 84 to 304 pins (see Table 2) Software design support and automatic place-and-route provided by the Altera® MAX+PLUS® II development system for Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and Veribest Note (1) 192Pin PGA 208Pin PQFP 225Pin BGA 232Pin PGA 240Pin PQFP 280Pin PGA 304Pin RQFP
Table 2. FLEX 8000 Package Options & I/O Pin Count Device 84Pin PLCC
68 68 68 112
100Pin TQFP
78 78 68
144Pin TQFP
160Pin PQFP
160Pin PGA
EPF8282A EPF8282AV EPF8452A EPF8636A EPF8820A EPF81188A EPF81500A Note:
(1)
120 118 120
120 136 152 136 152 148 152 184 184 181 208 208
FLEX 8000 device package types include plastic J-lead chip carrier (PLCC), thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat pack (RQFP), ball-grid array (BGA), and pin-grid array (PGA) packages.
General Description
Altera's Flexible Logic Element MatriX (FLEX®) family combines the benefits of both erasable programmable logic devices (EPLDs) and fieldprogrammable gate arrays (FPGAs). The FLEX 8000 device family is ideal for a variety of applications because it combines the fine-grained architecture and high register count characteristics of FPGAs with the high speed and predictable interconnect delays of EPLDs. Logic is implemented in LEs that include compact 4-input look-up tables (LUTs) and programmable registers. High performance is provided by a fast, continuous network of routing resources.
2
Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
FLEX 8000 devices provide a large number of storage elements for applications such as digital signal processing (DSP), wide-data-path manipulation, and data transformation. These devices are an excellent choice for bus interfaces, TTL integration, coprocessor functions, and high-speed controllers. The high-pin-count packages can integrate multiple 32-bit buses into a single device. Table 3 shows FLEX 8000 performance and LE requirements for typical applications. Table 3. FLEX 8000 Performance Application LEs Used A -2
16-bit loadable counter 16-bit up/down counter 24-bit accumulator 16-bit address decode 16-to-1 multiplexer 16 16 24 4 10 125 125 87 4.2 6.6
Speed Grade A-3
95 95 67 4.9 7.9
Units A-4
83 83 58 6.3 9.5 MHz MHz MHz ns ns
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FLEX 8000
All FLEX 8000 device packages provide four dedicated inputs for synchronous control signals with large fan-outs. Each I/O pin has an associated register on the periphery of the device. As outputs, these registers provide fast clock-to-output times; as inputs, they offer quick setup times. The logic and interconnections in the FLEX 8000 architecture are configured with CMOS SRAM elements. FLEX 8000 devices are configured at system power-up with data stored in an industry-standard parallel EPROM or an Altera serial configuration devices, or with data provided by a system controller. Altera offers the EPC1, EPC1213, EPC1064, and EPC1441 configuration devices, which configure FLEX 8000 devices via a serial data stream. Configuration data can also be stored in an industry-standard 32 K × 8 bit or larger configuration device, or downloaded from system RAM. After a FLEX 8000 device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. Because reconfiguration requires less than 100 ms, realtime changes can be made during system operation. For information on how to configure FLEX 8000 devices, go to the following documents:
Configuration Devices for APEX & FLEX Devices Data Sheet BitBlaster Serial Download Cable Data Sheet ByteBlasterMV Parallel Port Download Cable Data Sheet Application Note 33 (Configuring FLEX 8000 Devices) Application Note 38 (Configuring Multiple FLEX 8000 Devices)
Altera Corporation
3
FLEX 8000 Programmable Logic Device Family Data Sheet
FLEX 8000 devices contain an optimized microprocessor interface that permits the microprocessor to configure FLEX 8000 devices serially, in parallel, synchronously, or asynchronously. The interface also enables the microprocessor to treat a FLEX 8000 device as memory and configure the device by writing to a virtual memory location, making it very easy for the designer to create configuration software. The FLEX 8000 family is supported by Altera's MAX+PLUS II development system, a single, integrated package that offers schematic, text--including the Altera Hardware Description Language (AHDL), VHDL, and Verilog HDL--and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0, library of parameterized modules (LPM), VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industrystandard PC- and UNIX workstation-based EDA tools. The MAX+PLUS II software runs on Windows-based PCs and Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations. The MAX+PLUS II software interfaces easily with common gate array EDA tools for synthesis and simulation. For example, the MAX+PLUS II software can generate Verilog HDL files for simulation with tools such as Cadence Verilog-XL. Additionally, the MAX+PLUS II software contains EDA libraries that use device-specific features such as carry chains, which are used for fast counter and arithmetic functions. For instance, the Synopsys Design Compiler library supplied with the MAX+PLUS II development system includes DesignWare functions that are optimized for the FLEX 8000 architecture.
f Functional Description
For more information on the MAX+PLUS II software, go to the MAX+PLUS II Programmable Logic Development System & Software Data Sheet. The FLEX 8000 architecture incorporates a large matrix of compact building blocks called logic elements (LEs). Each LE contains a 4-input LUT that provides combinatorial logic capability and a programmable register that offers sequential logic capability. The fine-grained structure of the LE provides highly efficient logic implementation. Eight LEs are grouped together to form a logic array block (LAB). Each FLEX 8000 LAB is an independent structure with common inputs, interconnections, and control signals. The LAB architecture provides a coarse-grained structure for high device performance and easy routing.
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Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
Figure 1 shows a block diagram of the FLEX 8000 architecture. Each group of eight LEs is combined into an LAB; LABs are arranged into rows and columns. The I/O pins are supported by I/O elements (IOEs) located at the ends of rows and columns. Each IOE contains a bidirectional I/O buffer and a flipflop that can be used as either an input or output register. Figure 1. FLEX 8000 Device Block Diagram
I/O Element (IOE)
IOE IOE IOE IOE
IOE
IOE
IOE
IOE
Logic Array Block (LAB)
IOE
FastTrack Interconnect
IOE
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FLEX 8000
IOE
IOE
Logic Element (LE)
IOE
IOE
IOE
IOE
Signal interconnections within FLEX 8000 devices and between device pins are provided by the FastTrack Interconnect, a series of fast, continuous channels that run the entire length and width of the device. IOEs are located at the end of each row (horizontal) and column (vertical) FastTrack Interconnect path.
Altera Corporation
5
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