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Part: EPC4QC100
Category:
FPGAs/PLDs
-> FPGA (Field Programmable Gate Array)
Description: Enhanced Configuration Devices, 4-Mbit
Company: Altera Corporation
Datasheet: Download EPC4QC100 datasheet File size : 188 kB
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Datasheet text preview:
®
Enhanced Configuration Devices
(EPC4, EPC8 & EPC16)
Data Sheet
April 2002, ver. 2.0
Features
Preliminar y Information
Enhanced configuration devices include EPC4, EPC8, and EPC16 devices 4-, 8-, and 16-Mbit Flash memory devices that configure StratixTM, APEXTM II, APEX 20K, MercuryTM , ACEXTM 1K, and FLEX® 10K devices Compression increases effective configuration density of these devices up to 7, 15, or 30 Mbits Available in the 100-pin plastic quad flat pack (PQFP) package and the 88-pin Ultra FineLine BGATM package Standard Flash die and a controller die combined into one package VCCINT and VCCIO are both 3.3 V Supports true N-bit (N = 1, 2, 4, and 8) programmable logic device (PLD) concurrent configuration mode Configures multiple PLDs in parallel Supports an 8-bit parallel data output on every DCLK cycle Pin-selectable 2-ms or 100-ms power-on reset (POR) time Programmable clock speed with three clock modes for faster configuration time Internal oscillator defaults to 10 MHz Programmable internal oscillator for higher frequencies of 33, 50, and 66 MHz External clock source with frequencies up to 133 MHz EPC16 configuration device allows PLD or processor to access unused Flash memory locations via external flash interface Flash memory can hold up to eight pages of configuration files, enabling systems to reconfigure PLDs with different configuration files Flash block/sector protection capability (EPC16 configuration devices only) Compliant with IEEE Std. 1532 in-system programmability (ISP) specification Supports ISP via JamTM Standard Test and Programming Language (STAPL) Supports Joint Test Action Group (JTAG) boundary scan nINIT_CONF pin allows private JTAG instruction to initiate PLD configuration Programmable configuration done error detection capability Internal programmable weak pull-ups on nCS and OE pins, Flash address, and control lines, and bus hold on data line Standby mode with reduced power consumption
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Altera Corporation
DS-ECD-2.0
Enhanced Configuration Devices Data Sheet
Preliminary Information
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A future version of this data sheet will include more information on Stratix device support.
Architecture Description
The Altera® enhanced configuration devices support a single-device solution for very high-density PLDs while decreasing configuration time. The core of an enhanced configuration device is divided into two major blocks, the controller and the Flash memory. The Flash memory can be used for APEX II, APEX 20K, Mercury, ACEX, and FLEX 10K device configuration, and its unused locations can be used as memory storage for the PLD or processor. 1 All references to the direct Flash interface in this document are for EPC16 configuration devices only. For information on using Flash memory interface in the EPC4 or EPC8 configuration devices, please contact Altera Applications.
Figure 1 shows a block diagram of the enhanced configuration device's core blocks, their connection to the PLD, and their interface with the JTAG/ISP interface. Figure 1. Enhanced Configuration Device Block Diagram
JTAG/ISP Interface
Enhanced Configuration Device
Flash
Controller
PLD
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Altera Corporation
Preliminary Information
Enhanced Configuration Devices Data Sheet
Enhanced Configuration Device Controller Unit
The controller unit of the enhanced configuration device has a 3.3-V core and an I/O interface. The controller is a synchronous system that includes the following:
Power-on reset circuitry (POR) Internal oscillator (IOSC) Clock divider unit (CDU) Decompression engine PLD configuration unit (PCU) JTAG interface unit (JIU)
Figure 2 shows a block diagram of the enhanced configuration device controller unit. Figure 2. Enhanced Configuration Device Controller Unit Block Diagram
Page Mode Select TDI, TDO, TMS , TCK EXCLK (1)
Enhanced Configuration Device Controller
OE# WE# CE# WP# A[20:0] JIU 3 4
nINIT_CONF IOSC Oscillator INTOSC CDU
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nCONFIG
Tools
Flash Memory
16 DQ[15:0] 16 16 Decompression Engine Flash Data In Bus Flash Data Out Bus
DCLK
Divide by N
PLD
SYSCLK
Divide by M
DCLK Pause [7:0] 8
PCU 1 DATA[7:0]
DCLK
16 POR Unit POR RP# RD/BY# POR Counter Flash Reset PLD Reset [15:8]
DATA[7:0] CONF_DONE
nCS
7
OE
nSTATUS
PORSEL
Note to Figure 2:
(1) EXCLK should be connected to VCC or GND if it is not being used.
Altera Corporation
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Enhanced Configuration Devices Data Sheet
Preliminary Information
Power-On Reset Unit
The POR circuit keeps the system in reset until the power supply voltage levels have stabilized. The enhanced configuration device has two options for the POR time: the user can either keep the POR time at the 100-ms default value or reduce the POR time through the selectable input pin to 2 ms for applications that require fast power-up. The PORSEL input pin controls the POR reduction time from 100 ms to 2 ms. See Table 7 on page 28 for more information. The POR unit manages the controller's reset scheme. When the POR counter expires, the POR unit releases the OE pin. The POR time can be further extended from an external source by driving the OE pin low. 1 Do not execute JTAG or ISP instructions until POR is complete.
The enhanced configuration device reset can be divided into three categories:
The POR reset starts at initial power-up reset during VCC ramp or if VCC drops anytime after VCC has stabilized. The PLD initiates re-configuration by driving nSTATUS low, which occurs if the PLD detects a cyclic redundancy check (CRC) error or if the nCONFIG input pin is asserted in the PLD. The controller detects an error and asserts the OE to initiate reconfiguration of APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX 10K devices when the auto restart upon error option is enabled in software.
Internal Oscillator
Frequencies for the internal oscillator (IOSC) of the enhanced configuration device, which supports four modes of internal clock frequencies, are shown in Table 1. The user can program the oscillator, which is controlled by option bits through the software. Table 1. Internal Oscillator Frequencies Mode
A B C D
Min (MHz)
6.4 21.0 32.0 42.0
Typ (MHz)
8.0 26.5 40.0 53.0
Max (MHz)
10.0 33.0 50.0 66.0
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Altera Corporation
Preliminary Information
Enhanced Configuration Devices Data Sheet
Clock Divider Unit
The CDU generates SYSCLK and DCLK for the controller by dividing the internal oscillator clock (INTOSC) or external clock (EXCLK). The CDU's clock division architecture has two dividers. The first divider (N) divides down the selected reference clock to generate DCLK. The second divider (M) divides down DCLK to generate SYSCLK. Each divider contains a 1 to 16 integer divider. Both a 1.5 divider and a 2.5 divider are also implemented in the first divider (N), but the second divider (M) can only divide integers. As a default from power-up, the INTOSC is in mode A, the first divider is set to divide by one to generate the DCLK, and the second divider is set to divide by two to generate the SYSCLK (see Figure 3). The default duty cycle for all clock divisions other than non-integer divisions is 50% (for the non-integer dividers, the duty cycle will not be 50%). For integer divisions, the CDU allows the duty cycle of DCLK and SYSCLK to be programmable by setting appropriate option bits through the software. The DCLK frequency is limited by the maximum DCLK frequency of the PLD, but the SYSCLK frequency is limited by the maximum Flash performance (about 10 MHz). Therefore, DCLK and SYSCLK might run at different frequencies. See Figure 3 for details on the CDU.
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The maximum DCLK frequency for each PLD family is specified in Application Note 116 (Configuring SRAM-Based LUT Devices). Figure 3. Clock Divider Unit
CDU INTOSC EXCLK
Divide by N DCLK
Divide by M SYSCLK
Altera Corporation
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