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Part: EP1S40B956C6
Category:
FPGAs/PLDs
-> FPGA (Field Programmable Gate Array)
Description: Stratix Device Family 1.5V, 10-Mb RAM, Lvds, DSP
Company: Altera Corporation
Datasheet: Download EP1S40B956C6 datasheet File size : 709 kB
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Stratix Device Handbook, Volume 1
101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com
S5V1-1.2
Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Printed on recycled paper
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Contents
Chapter Revision Dates ........ vii About this Handbook ....... ix
How to Find Information ...... ix How to Contact Altera ........... ix Typographic Conventions ...... x
Section I. Stratix Device Family Data Sheet
Revision History .......... Part I1
Chapter 1. Introduction
Introduction ........... 11 Features ......... 12
Chapter 2. Stratix Architecture
Functional Description ........ 21 Logic Array Blocks .............. 23 LAB Interconnects .......... 24 LAB Control Signals ....... 25 Logic Elements ...... 26 LUT Chain & Register Chain .......... 28 addnsub Signal ...... 28 LE Operating Modes ...... 28 Clear & Preset Logic Control ........ 213 MultiTrack Interconnect ............ 214 TriMatrix Memory ............. 221 Memory Modes ............. 222 Parity Bit Support ......... 224 Shift Register Support ........... 224 Memory Block Size ....... 225 Independent Clock Mode ..... 243 Input/Output Clock Mode .. 245 Read/Write Clock Mode ...... 247 Single-Port Mode .......... 249 Digital Signal Processing Block ......... 249 Multiplier Block ............ 255 Adder/Output Blocks .......... 259 Modes of Operation ..... 262
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Contents
Stratix Device Handbook, Volume 1
DSP Block Interface ...... 268 PLLs & Clock Networks ............ 271 Global & Hierarchical Clocking ......... 271 Enhanced & Fast PLLs .......... 278 Enhanced PLLs ............. 284 Fast PLLs ......... 297 I/O Structure ..... 2101 Double-Data Rate I/O Pins ......... 2108 External RAM Interfacing .. 2110 Programmable Drive Strength ......... 2126 Open-Drain Output .... 2127 Slew-Rate Control ...... 2127 Bus Hold ....... 2127 Programmable Pull-Up Resistor ...... 2128 Advanced I/O Standard Support .... 2128 Terminator Technology ...... 2133 MultiVolt I/O Interface ...... 2136 High-Speed Differential I/O Support ........... 2137 Dedicated Circuitry .... 2143 Byte Alignment ........... 2146 Power Sequencing & Hot Socketing ..... 2146
Chapter 3. Configuration & Testing
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support .......... 31 SignalTap Embedded Logic Analyzer ...... 35 Configuration ........ 35 Operating Modes ............ 35 Configuring Stratix FPGAs with JRunner ... 37 Configuration Schemes .......... 37 Partial Reconfiguration ........... 38 Remote Update Configuration Modes ......... 38 Temperature Sensing Diode ...... 312
Chapter 4. DC & Switching Characteristics
Operating Conditions ......... 41 Power Consumption ......... 415 Timing Model ...... 417 Preliminary & Final Timing .......... 417 Performance ... 418 Internal Timing Parameters .......... 421 External Timing Parameters ......... 429 External I/O Delay Parameters .......... 453 Maximum Input & Output Clock Rates ..... 463 High-Speed I/O Timing ....... 474 PLL Timing ..... 479
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Contents
Contents
Chapter 5. Reference & Ordering Information
Software ........ 51 Device Pin-Outs .... 51 Ordering Information ......... 51
Index
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