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Part: AM79C864A
Category:
Communication
-> Network
-> FDDI
Description: Fddi Physical Layer Controller (plc) With Scramble
Company: Advanced Micro Systems, Inc.
Datasheet: Download AM79C864A datasheet File size : 1108 kB
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D
PRELIMINARY
Am79C864A
Physical Layer Controller With Scrambler (PLC-S)
ISTINCTIVE CHARACTERISTICS
s Implements FDDI PHY layer protocol for ISO standard (FDDI) 9314-1 s Implements ANSI standard Stream Cipher Scrambling/Descrambling s Hardware Physical Connection Management (PCM) support s Performs Physical Connection insertion and removal s On-chip Link Error Monitor (LEM) and Link Confidence Test (LCT) s Line state detection s Repeat filter
Advanced Micro Devices
s Elasticity buffer and smoother functions s 4B/5B encoding/decoding s Full duplex operation s Data framing s Built-in Self Test
GENERAL DESCRIPTION
The Physical Layer Controller with Scrambler (PLC-S) is a CMOS device which along with Physical Data Transmitter (PDT) and Physical Data Receiver (PDR) implements the Physical Layer Protocol (PHY) and portions of the Station Management (SMT) of the ANSI Fiber Distributed Data Interface (FDDI) standard. The PLC-S, PDT and PDR are collectively known as the AmPHY. PHY functions performed by the PLC-S include framing of data on symbol pair boundaries, the elasticity buffer function, the smoothing function, 4B/5B encoding and decoding of symbols, line state detection, the repeat filter function, and Stream Cipher Scrambling/Descrambling. SMT functions performed include Physical Connection Management (PCM), Physical Connection insertion and removal and Link Error Monitor. The PLC-S chip receives symbol-wide (5 bits) data along with a 25 MHz recovered clock from the PDR chip and searches for a JK symbol pair (also known as Starting Delimiter). It uses the starting delimiter to establish byte boundaries (i.e. to frame the data). Framed data is then sent to the Elasticity Buffer which serves to compensate for the frequency difference between the recovered clock and the local clock. Data output by the Elasticity Buffer is checked by the Smoother and when necessary, Idle symbols are inserted between frames to maintain a minimum number of Idle symbols in the interframe gap. The data is then decoded and sent to the Media Access Control (MAC) chip. The data is byte-wide (10 bits) and is clocked by a 12.5 MHz local clock.
Publication# 15535 Rev. B Amendment /0 Issue Date: November 1993
The PLC-S receives byte-wide data from the MAC at 12.5 million bytes per second, encodes the data and sends out symbol-wide data at 25 million symbols per second to PDT chip. In the transmit path, there is a Repeat Filter to detect corrupted symbols and convert them into the specified pattern of Halt and Idle symbols. The Repeat Filter in each PLC-S chip converts the last byte of a frame fragment into Idle symbols and thus eventually removing fragments from the ring. The PLC-S device includes a Stream Cipher Scrambler/ Descrambler as prescribed in the ANSI TP-PMD standard for transmission over twisted-pair cable. For copper-based designs, the scrambler/descrambler may be enabled either through software or hardware. For fiber-based designs, the scrambler/descrambler is disabled by default. For a detailed description of the ANSI-compliant copper FDDI system using the PLC-S device, refer to AMD PID #18258A, Implementing FDDI over Copper; The ANSI X3T9.5 Standard. The PCM initializes the connection of neighboring PHYs and manages the PHY signaling. PCM consists of the PCM state machine, which determines the timing and state requirements for PCM, and the PCM Pseudo Code, which provides the information to be communicated to the neighboring PCM and specifies the connection policies. The PLC-S chip contains the PCM State Machine, while the PCM Pseudo Code is controlled by software. The PCM State Machine communicates with other PCMs using a bit signaling mechanism whereby certain line states are received and transmitted. The PCM also makes use of the Link Error Monitor in the
This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
3-3
AMD
PRELIMINARY The Node Processor Interface in the PLC-S consists of several control and status registers. The PLC-S also contains error and special event counters, Built In Self Test (BIST) logic, Boundary Scan logic, and several data loopback multiplexers so that internal data paths may be reconfigured for test purposes.
PLC-S chip during Link Confidence Test and after the link has been formed, to detect a noisy link. The PLC-S contains a Line State Machine for detecting received line states and a Data Stream Generator for transmitting the various line states. The PLC-S also contains a state machine called Physical Connection Insertion (PCI) which is used in Physical Connection insertion and removal. It performs the necessary ring scrubbing and data path switching.
PLC-S BLOCK DIAGRAM
SCRM
Programmable FOTOFF Control
FOTOFF
TX 90 ITDAT TXPAR NPADDR 4-0 NP 15-0 PLC-S Core
TDAT 40 Stream Cipher Scrambler
LSCLK Control Signals CIPHER_ LOOPBACK MUX
RX 90 IRDAT RXPAR
Stream Cipher Descrambler
RDAT 40
RSCLK (Optional) Signal_Detect Control SDO
15535B-1
See next page for the PLC-S Core block diagram
3-4
The SUPERNET 2 Family for FDDI 1994 Data Book
PRELIMINARY
AMD
PLC-S CORE BLOCK DIAGRAM
Receive Data Input IRDAT
EB Local Lbmux
Framer
Elasticity LM Buffer/ Local Smoother Lbmux
Decoder
Bypass Mux
Scrub Mux
Receive Data Output RX
5
11
Idles Misc Status and Control
NP PCM 16 NPADDR 5 Error Counters and Timers Line State Machine
Control Signals
NP Interface
Built-in Self Test
Repeat Filter
ITDAT
TX
5 Transmit Data Output Test Data Mux Encoder Data Stream Generator Remote Loopback Mux
11 Transmit Data Input
15535B-2
Am79C864A
3-5
AMD
PRELIMINARY
TABLE OF CONTENTS
DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 PLC-S BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 PLC-S CORE BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 CONNECTION DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 PIN DESIGNATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 LOGIC SYMBOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Node Processor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 PLC-S Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 Physical Connection Management Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 Physical Connection Management Timing Parameters . . . . . . . . . . . . . . . . . . . . . . 3-28 Physical Connection Management Bit Signaling Registers . . . . . . . . . . . . . . . . . . . 3-28 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30 Built In Self Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 Framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 Elasticity Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 Smoother Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 Line State Machine (LSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 Link Error Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 Physical Connection Management (PCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 PCM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35 PCM State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35 Pseudo Code Bit Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35 PCI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 PCI State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38
3-6
The SUPERNET 2 Family for FDDI 1994 Data Book
PRELIMINARY
AMD
TABLE OF CONTENTS
Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40 Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 Repeat Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 Data Stream Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42 Data Path MUXes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43 EB Local Loopback MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43 Cipher Loopback MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43 LM Local Loopback MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43 Bypass MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43 Remote Loopback MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43 Scrub MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43 Test Data MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44 Data Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44 Receive Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44 Receive Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44 Transmit Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44 Transmit Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44 Built In Self Test (BIST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44 BIST Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44 Counter Segmentation Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 Boundary Scan Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46 OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46 DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46 CAPACITANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46
SWITCHING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47 SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48 SWITCHING TEST CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52 SWITCHING TEST WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53
Am79C864A
3-7
Others parts begin by am
AM-1 AM-2 AM-3 AM-4 AM-5 AM-6 AM-7 AM-8 AM-9 AM-10 AM-11 AM-12 AM-13 AM-14 AM-15 AM-16 AM-17 AM-18 AM-19 AM-20 AM-21 AM-22 AM-23 AM-24 AM-25 AM-26 AM-27 AM-28 AM-29 AM-30 AM-31 AM-32 AM-33 AM-34 AM-35 AM-36 AM-37 AM-38 AM-39 AM-40 AM-41 AM-42 AM-43 AM-44 AM-45 AM-46 AM-47 AM-48 AM-49 AM-50 AM-51 AM-52 AM-53 AM-54 AM-55 AM-56 AM-57 AM-58 AM-59 AM-60 AM-61 AM-62 AM-63 AM-64 AM-65 AM-66 AM-67 AM-68 AM-69 AM-70 AM-71 AM-72 AM-73 AM-74 AM-75 AM-76 AM-77 AM-78 AM-79 AM-80 AM-81 AM-82 AM-83 AM-84 AM-85 AM-86 AM-87 AM-88 AM-89 AM-90 AM-91 AM-92 AM-93 AM-94 AM-95 AM-96 AM-97 AM-98 AM-99 AM-100 AM-101 AM-102 AM-103 AM-104 AM-105
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