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Part: AM53C94
Category:
Interface and Interconnect
-> SCSI
-> Controller
Description: High Performance Scsi Controller
Company: Advanced Micro Systems, Inc.
Datasheet: Download AM53C94 datasheet File size : 342 kB
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Datasheet text preview:
D
PRELIMINARY
Am53C94/Am53C96
High Performance SCSI Controller
ISTINCTIVE CHARACTERISTICS
s s s s s s s s s Pin/function compatible with NCR53C94/53C96 AMD's Patented GLITCH EATERTM Circuitry on REQ and ACK inputs 5 Mbytes per second synchronous SCSI transfer rate 20 Mbytes per second DMA transfer rate 16-bit DMA Interface plus 2 bits of parity Flexible three bus architecture Single ended SCSI bus supported by Am53C94 Single ended and differential SCSI bus supported by Am53C96 Selection of multiplexed or non-multiplexed address and data bus s s s s s s s s
Advanced Micro Devices
High current drivers (48 mA) for direct connection to the single ended SCSI bus Supports Disconnect and Reselect commands Supports burst mode DMA operation with a threshold of 8 Supports 3-byte-tagged queuing as per the SCSI-2 specification Supports group 2 and 5 command recognition as per the SCSI-2 specification Advanced CMOS process for low power consumption Am53C94 available in 84-pin PLCC package Am53C96 available in 100-pin PQFP package
GENERAL DESCRIPTION
The High Performance SCSI Controller (HPSC) has a flexible three bus architecture. The HPSC has a 16-bit DMA interface, an 8 bit host data interface and an 8-bit SCSI data interface. The HPSC is designed to minimize host intervention by implementing common SCSI sequences in hardware. An on-chip state machine reduces protocol overheads by performing the required sequences in response to a single command from the host. Selection, reselection, information transfer and disconnection commands are directly supported. The 16-byte-internal FIFO further assists in minimizing host involvement. The FIFO provides a temporary storage for all command, data, status and message bytes as they are transferred between the 16 bit host data bus and the 8 bit SCSI data bus. During DMA operations the FIFO acts as a buffer to allow greater latency in the DMA channel. This permits the DMA channel to be suspended for higher priority operations such as DRAM refresh or reception of an ISDN packet. Parity on the DMA bus is optional. Parity can either be generated and checked or it can be simply passed through. The patented GLITCH EATER Circuitry in the High Performance SCSI Controller detects signal changes that are less than or equal to 15 ns and filters them out. It is designed to dramatically increase system performance and reliability by detecting and filtering glitches that can cause system failure. The GLITCH EATER Circuitry is implemented on the ACK and REQ lines only. These lines often encounter many electrical anomalies which degrade system performance and reliability. The two most common are Reflections and Voltage Spikes. Reflections are a result of high current SCSI signals that are mismatched by stubs, cables and terminators. These reflections vary from application to application and can trigger false handshake signals on the ACK and REQ lines if the voltage amplitude is at the TTL threshold levels. Spikes are generated by high current SCSI signals switching concurrently. On the control signals (ACK and REQ) they can trigger false data transfers which result in loss of data, addition of random data, double clocking and reduced system reliability. AMD's GLITCH EATER Circuitry helps maintain excellent system performance by treating the glitches. Refer to the diagram on the next page.
This document contains information on a product under development at Advanced Micro Devices Inc. The information is intended to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Publication# 16506 Rev. C Issue Date: May 1993
Amendment /0
AMD
PRELIMINARY
GLITCH EATER Circuitry in SCSI Environment
>15 ns SCSI Environment <15 ns
Valid Signal
Glitches
Device without the GLITCH EATER Circuit
ACK or REQ Input Glitches pass through as valid signals
AMD's Device with the GLITCH EATER Circuit
ACK or REQ Input Glitches Filtered Valid Signal Passes
16506C-1
SYSTEM BLOCK DIAGRAM
4 CPU 16 8
Addr 9 Data Am53C94/96 9 16 SCSI Control SCSI Data
DMA
16
DMA
Memory
16
16506C-2
2
Am53C94/Am53C96
PRELIMINARY
AMD
SYSTEM BUS MODE DIAGRAMS
BUSMD 1 BUSMD 0 DMAWR WR RD Address Bus A 30 8-Bit Data Bus DMA 70 DACK DREQ Host Processor Bus Controller
Am53C94/96
DMA Controller
Bus Mode 0
16506C-3
VDD
BUSMD 1 BUSMD 0
DMAWR WR RD Address Bus A 30 Data Bus DMA 150 Host Processor Bus Controller
Am53C94/96
DACK
DREQ
16
8
DMA Controller
16506C-4
Bus Mode 1
Am53C94/Am53C96
3
AMD
PRELIMINARY
SYSTEM BUS MODE DIAGRAMS
VDD
BUSMD 1 BUSMD 0
WR RD ALE 8-Bit Data Bus AD 70 Host Processor
Am53C94/96
16-Bit Data Bus DMA 150 AS0 BHE DMARD DMAWR DREQ DACK
16506C-5
DMA Controller
Bus Mode 2
VDD
BUSMD 1 BUSMD 0
WR RD Address Bus A 30 8-Bit Data Bus AD 70 Host Processor
Am53C94/96
16-Bit Data Bus DMA 150 DMAWR DREQ DACK DMA Controller
16506C-6
Bus Mode 3
4
Am53C94/Am53C96
PRELIMINARY
AMD
BLOCK DIAGRAM
Data Tranceivers
18 DMA 15-0 DMAP1-0 DMA Control 4 Bus Interface Unit 8
16 x 9 FIFO (including parity)
18
9
SCSI Bus Data + Parity (Single Ended) SCSI Bus Data + Parity Direction Control
Parity Logic
9
AD 7-0 Host Control CS BUSMD1-0 DFMODE CLK RESET 6
MUX
SCSI Control
8
Register B ank
S Main equencer 9 7 SCSI Control D SCSI Control irection Control
8 S SCSI equencer
16506C-7
Am53C94/Am53C96
5
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