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Part: AM29F400BT-45
Category:
Memory
-> Flash
-> Parallel Flash
-> 4M
Description: 4 Megabit CMOS 5.0 Volt-only Sector Erase Flash Memory: 512kx8/256kx16
Company: Advanced Micro Systems, Inc.
Datasheet: Download AM29F400BT-45 datasheet File size : 1438 kB
Request For quote: Find where to buy AM29F400BT-45
Datasheet text preview:
Am29F400B
4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s Single power supply operation -- 5.0 volt-only operation for read, erase, and program operations -- Minimizes system level requirements s Manufactured on 0.32 µm process technology -- Compatible with 0.5 µm Am29F400 device s High performance -- Access times as fast as 45 ns s Low power consumption (typical values at 5 MHz) -- 1 µA standby mode current -- 20 mA read current (byte mode) -- 28 mA read current (word mode) -- 30 mA program/erase current s Flexible sector architecture -- One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and seven 64 Kbyte sectors (byte mode) -- One 8 Kword, two 4 Kword, one 16 Kword, and seven 32 Kword sectors (word mode) -- Suppor ts full chip erase -- Sector Protection features: A hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked via programming equipment Temporar y Sector Unprotect feature allows code changes in previously locked sectors s Top or bottom boot block configurations available s Embedded Algorithms -- Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors -- Embedded Program algorithm automatically writes and verifies data at specified addresses s Minimum 1,000,000 program/erase cycles per sector guaranteed s 20-year data retention at 125°C -- Reliable operation for the life of the system s Package option -- 48-pin TSOP -- 44-pin SO -- Known Good Die (KGD) (see publication number 21258) s Compatibility with JEDEC standards -- Pinout and software compatible with singlepower-supply Flash -- Superior inadvertent write protection s Data# Polling and toggle bits -- Provides a software method of detecting program or erase operation completion s Ready/Busy# pin (RY/BY#) -- Provides a hardware method of detecting program or erase cycle completion s Erase Suspend/Erase Resume -- Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation s Hardware reset pin (RESET#) -- Hardware method to reset the device to reading array data
This Data Sheet states AMD's current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 21505 Rev: E Amendment/+1 Issue Date: November 30, 2000
GENERAL DESCRIPTION
T h e Am29F400B is a 4 Mbit, 5.0 volt-only Flash memor y organized as 524,288 bytes or 262,144 words. The device is offered in 44-pin SO and 48-pin TSOP packages. The device is also available in Known Good Die (KGD) form. For more information, refer to publication number 21258. The word-wide data (x16) appears on DQ15DQ0; the byte-wide (x8) data appears on DQ7 DQ0. This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply. A 12.0 V VPP is not required for write or erase operations. The device can also be programmed in standard EPROM programmers. T h i s device is manufactured using AMD's 0.32 µm process technology, and offers all the features and benefits of the Am29F400, which was manufactured using 0.5 µm process technology. The standard device offers access times of 45, 50, 55, 70, 90, 120, and 150 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. T h e device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Comm a n d s are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that co ntr ol s the erase and programming circuitry. Write cycles also internally latch addresses and data needed fo r the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program c o m m a n d sequence. This initiates the Embedded Program algorithm--an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. D e v i c e erasure occurs by executing the erase c o m m a n d sequence. This initiates the Embedded Erase algorithm--an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# p i n , or by reading the DQ7 (Data# Polling) and D Q 6 / D Q 2 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the d a t a contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. T h e system can place the device into the standby mode. Power consumption is greatly reduced in this mode. A M D 's Flash technology combines years of Flash m e m o r y manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.
2
Am 2 9 F 4 0 0 B
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 4 4 5 6 6 7 8 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 22
Figure 6. Maximum Negative Overshoot Waveform .... 22 Figure 7. Maximum Positive Overshoot Waveform ...... 22
Table 1. Am29F400B Device Bus Operations .......... 8
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23 TTL/NMOS Compatible .......... 23 CMOS Compatible ......... 24 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 8. Test Setup..... 25 Table 7. Test Specifications .. 25
Word/Byte Configuration .......... 8 Requirements for Reading Array Data .... 8 Writing Commands/Command Sequences ...... 8 Program and Erase Operation Status ..... 9 Standby Mode ........ 9 RESET#: Hardware Reset Pin ....... 9 Output Disable Mode ....... 9
Table 2. Am29F400BT Top Boot Block Sector Address Table ....... 10 Table 3. Am29F400BB Bottom Boot Block Sector Address Table.. 10
Key to Switching Waveforms. . . . . . . . . . . . . . . . 25 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26 Read Operations ........... 26
Figure 9. Read Operations Timings ..... 26
Hardware Reset (RESET#) .... 27
Figure 10. RESET# Timings .......... 27
Word/Byte Configuration (BYTE#)
..... 28
Autoselect Mode ............ 10
Table 4. Am29F400B Autoselect Codes (High Voltage Method) .... 11
Figure 11. BYTE# Timings for Read Operations.... 28 Figure 12. BYTE# Timings for Write Operations.... 28
Sector Protection/Unprotection ..... 11 Temporary Sector Unprotect ........ 11
Figure 1. Temporary Sector Unprotect Operation... 11
Erase/Program Operations ..... 29
Figure 13. Program Operation Timings......... Figure 14. Chip/Sector Erase Operation Timings .. Figure 15. Data# Polling Timings (During Embedded Algorithms). Figure 16. Toggle Bit Timings (During Embedded Algorithms)...... Figure 17. DQ2 vs. DQ6........ 30 31 32 32 33
Hardware Data Protection ...... 12
Low VCC Write Inhibit .... 12 Write Pulse "Glitch" Protection ........ 12 Logical Inhibit .......... 12 Power-Up Write Inhibit ........... 12
Temporary Sector Unprotect ........ 33
Figure 18. Temporary Sector Unprotect Timing Diagram ..... 33
Command Definitions . . . . . . . . . . . . . . . . . . . . . 13 Reading Array Data ....... 13 Reset Command ............ 13 Autoselect Command Sequence ........... 13 Word/Byte Program Command Sequence ..... 13
Figure 2. Program Operation .......... 14
Alternate CE# Controlled Erase/Program Operations ... 34
Figure 19. Alternate CE# Controlled Write Operation Timings ...... 35
Chip Erase Command Sequence .......... 14 Sector Erase Command Sequence ....... 14 Erase Suspend/Erase Resume Commands ... 16
Figure 3. Erase Operation...... 16 Table 5. Am29F400B Command Definitions.. 17
Write Operation Status . . . . . . . . . . . . . . . . . . . . 18 DQ7: Data# Polling ........ 18
Figure 4. Data# Polling Algorithm ......... 18
RY/BY#: Ready/Busy# .. 19 DQ6: Toggle Bit I ........... 19 DQ2: Toggle Bit II .......... 19 Reading Toggle Bits DQ6/DQ2 .... 19 DQ5: Exceeded Timing Limits ...... 20 DQ3: Sector Erase Timer ....... 20
Figure 5. Toggle Bit Algorithm......... 20 Table 6. Write Operation Status...... 21
Erase and Programming Performance . . . . . . . . 36 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 36 TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 36 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 37 TS 048--48-Pin Standard Thin Small Outline Package ......... 37 TSR048--48-Pin Reverse Thin Small Outline Package ......... 38 SO 044--44-Pin Small Outline Package ........ 39 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 40 Revision A (August 1997) ....... 40 Revision B (October 1997) ..... 40 Revision C (January 1998) ..... 40 Revision C+1 (February 1998) ..... 40 Revision C+2 (April 1998) ....... 40 Revision C+3 (June 1998) ...... 40 Revision C+4 (August 1998) ......... 41 Revision D (January 1999) ..... 41 Revision D+1 (July 2, 1999) ......... 41 Revision E (November 15, 1999) ........... 41 Revision E+1 (November 30, 2000) ...... 41
Am29F400B
3
PRODUCT SELECTOR GUIDE
Family Part Number Speed Option VCC = 5.0 V ± 5% VCC = 5.0 V ± 10% Max access time, ns (tACC) Max CE# access time, ns (tCE) Max OE# access time, ns (tOE) 45 45 30 50 50 30 -45 -50 -55 -55 55 55 30 -70 70 70 30 -90 90 90 35 -120 12 0 120 50 -150 150 150 55 Am29F400B
Note: See "AC Characteristics" for full specifications.
BLOCK DIAGRAM
RY/BY# VC C V SS RESET# Erase Voltage Generator Input/Output Buffers Sector Switches DQ0DQ15 (A-1)
WE# BYTE#
State Control Command Register
PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE# OE#
STB VCC Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0A17
4
Am 2 9 F 4 0 0 B
CONNECTION DIAGRAMS
T h i s device is also available in Known Good Die (KGD) form. Refer to publication number 21258 for more infor mation.
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# NC A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48-Pin TSOP--Standard Pinout
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48-Pin TSOP--Reverse Pinout
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# NC A17 A7 A6 A5 A4 A3 A2 A1
Am29F400B
5
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