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Part: AM29F200AT-55
Category:
Memory
-> Flash
-> Parallel Flash
-> 2M
Description: 2 Megabit (256 K X 8-bit/128 K X 16-bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory
Company: Advanced Micro Systems, Inc.
Datasheet: Download AM29F200AT-55 datasheet File size : 1438 kB
Request For quote: Find where to buy AM29F200AT-55
Datasheet text preview:
PRELIMINARY
Am29F200A
2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s 5.0 V ± 10% for read and write operations -- Minimizes system level power requirements s High performance -- Access times as fast as 55 ns s Low power consumption -- 20 mA typical active read current (byte mode) -- 28 mA typical active read current for (word mode) -- 30 mA typical program/erase current -- 1 µA typical standby current s Sector erase architecture -- One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and three 64 Kbyte sectors (byte mode) -- One 8 Kword, two 4 Kword, one 16 Kword, and three 32 Kword sectors (word mode) -- Suppor ts full chip erase -- Sector Protection features: A hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked via programming equipment Temporar y Sector Unprotect feature allows code changes in previously locked sectors s Top or bottom boot block configurations available s Embedded Algorithms -- Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors -- Embedded Program algorithm automatically writes and verifies data at specified addresses s Minimum 100,000 write/erase cycles guaranteed s Package options -- 44-pin SO -- 48-pin TSOP s Compatible with JEDEC standards -- Pinout and software compatible with single-power-supply flash -- Superior inadvertent write protection s Data# Polling and Toggle Bit -- Detects program or erase cycle completion s Ready/Busy# output (RY/BY#) -- Hardware method for detection of program or erase cycle completion s Erase Suspend/Erase Resume -- Suppor ts reading data from a sector not being erased s Hardware RESET# pin -- Resets internal state machine to the reading array data
Publication# 20637 Rev: B Amendment/+4 Issue Date: January 3, 2000
PRELIMINARY
GENERAL DESCRIPTION
The Am29F200A is a 2 Mbit, 5.0 Volt-only Flash memory organized as 262,144 bytes or 131,072 words. The 8 bits of data appear on DQ0DQ7; the 16 bits on DQ0 DQ15. The Am29F200A is offered in 44-pin SO and 48-pin TSOP packages. This device is designed to be programmed in-system with the standard system 5.0 vo lt V C C supply. A 12.0 volt VPP is not required for program or erase operations. The device can also be reprogrammed in standard EPROM programmers. T h e standard device offers access times of 55, 70, 9 0, 12 0, an d 15 0 n s, allowin g op era tio n of h ig h - s p e e d microprocessors without wait states. To e l i m i n a t e bus contention the device has separate c h i p enable (CE#), write enable (WE#) and output e n a bl e (OE#) controls. The device requires only a single 5.0 volt power supply for both read and write functions. Internally genera t e d and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents ser ve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program c o m m a n d sequence. This initiates the Embedded Program algorithm--an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase a lg o r i t h m -- a n internal algorithm that automatically p r e p r o g r a m s the array (if it is not already programmed) before executing the erase operation. Duri n g erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the d a t a contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memor y. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The system can place the device into the standby mode. Power consumption is greatly reduced in this mode. AMD's Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultan e o u s l y via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.
2
Am 2 9 F 2 0 0 A
PRELIMINARY
PRODUCT SELECTOR GUIDE
Family Part Number Speed Option VCC = 5.0 V ± 5% VCC = 5.0 V ± 10% 55 55 30 -55 -70 70 70 30 -90 90 90 35 -120 120 120 50 -150 150 150 55 Am29F200A
Max access time, ns (tACC) Max CE# access time, ns (tCE) Max OE# access time, ns (tOE)
BLOCK DIAGRAM
DQ0DQ15 VC C VSS RY/BY# Buffer RY/BY# Erase Voltage Generator Input/Output Buffers
WE# BYTE# RESET#
State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE# OE#
STB VCC Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0A16 A-1
20637B-1
Am29F200A
3
PRELIMINARY
CONNECTION DIAGRAMS
NC RY/BY# NC A7 A6 A5 A4 A3 A2 A1 A0 CE# VSS OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
SO
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
RESET# WE# A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC
20637B-2
4
Am 2 9 F 2 0 0 A
PRELIMINARY
CONNECTION DIAGRAMS
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# NC NC A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Standard TSOP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
20637B-3
A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Reverse TSOP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# NC NC A7 A6 A5 A4 A3 A2 A1
20637B-4
Am29F200A
5
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