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Part: AM28F512A-70
Category:
Memory
-> Flash
-> Parallel Flash
-> 512K
Description: 512k (64kx8-bit) CMOS 12.0 Volt, Bulk Erase Flash Memory With Embedded Algorithms
Company: Advanced Micro Systems, Inc.
Datasheet: Download AM28F512A-70 datasheet File size : 427 kB
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Datasheet text preview:
FINAL
Am28F512A
512 Kilobit (64 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms
DISTINCTIVE CHARACTERISTICS
s High performance -- 70 ns maximum access time s CMOS low power consumption -- 30 mA maximum active current -- 100 µA maximum standby current -- No data retention power consumption s Compatible with JEDEC-standard byte-wide 32-Pin EPROM pinouts -- 32-pin PDIP -- 32-pin PLCC -- 32-pin TSOP s 100,000 write/erase cycles minimum s Write and erase voltage 12.0 V -5% s Latch-up protected to 100 mA from -1 V to VCC +1 V s Embedded Erase Electrical Bulk Chip-Erase -- Two seconds typical chip-erase including pre-programming s Embedded Program -- 4 µs typical byte-program including time-out -- One second typical chip program s Command register architecture for microprocessor/microcontroller compatible write interface s On-chip address and data latches s Advanced CMOS flash memory technology -- Low cost single transistor memory cell s Embedded algorithms for completely self-timed write/erase operations
GENERAL DESCRIPTION
T h e Am28F512A is a 512 Kbit Flash memory organized as 64 Kbytes of 8 bits each. AMD's Flash memories offer the most cost-effective and reliable read/write non- volatile random access memory. The Am28F512A is packaged in 32-pin PDIP, PLCC, and TSOP versions. It is designed to be reprogrammed and erased in-syst e m or in standard EPROM programmers. The Am28F512A is erased when shipped from the factory. The standard Am28F512A offers access times as fast as 70 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the Am28F512A has separate chip enable (CE#) and output enable (OE#) controls. AMD's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The Am28F512A uses a command register to manage this functionality, while maintaining a JEDEC Flash standard 32-pin pinout. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming. AMD's Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The AMD cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low intern a l electr i c fields for erase a n d programmi n g operations produces reliable cycling. The Am28F512A uses a 12.0V± 5% VPP high voltage input to perform the erase and programming functions. The highest degree of latch-up protection is achieved with AMD's proprietary non-epi process. Latch-up protection is provided for stresses up to 100 milliamps on address and data pins from 1 V to VCC +1 V.
Embedded Program
The Am28F512A is byte programmable using the Embedded Programming algorithm. The Embedded Programming algorithm does not require the system to time -out or verify the data programmed. The typical room temperature programming time of the Am28F512A is one second.
Embedded Erase
T h e entire chip is bulk erased using the Embedded Erase algorithm. The Embedded Erase algorithm automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are
Publication# 18880 Rev: C Amendment/+2 Issue Date: April 1998
controlled internal to the device. Typical erasure at room temperature is accomplished in two seconds, including programming.
AMD's Am28F512A is entirely pin and software comp a t i b l e with AMD Am28F020A, Am28F010A, and Am28F256A Flash memories.
Comparing Embedded Algorithms with Flasherase and Flashrite Algorithms
Am28F512A with Embedded Algorithms Embedded Programming Algorithm vs. Flashrite Programming Algorithm AMD's Embedded Programming algorithm requires the user to only write a program set-up command and a program command (program data and address). The device automatically times the programming pulse width, verifies the programming, and counts the number of sequences. A status bit, Data# Polling, provides the user with the programming operation status. Am28F512 using AMD Flashrite and Flasherase Algorithms The Flashrite Programming algorithm requires the user to write a program set-up command, a program command, (program data and address), and a program verify command, followed by a read and compare operation. The user is required to time the programming pulse width in order to issue the program verify command. An integrated stop timer prevents any possibility of overprogramming. Upon completion of this sequence, the data is read back from the device and compared by the user with the data intended to be written; if there is not a match, the sequence is repeated until there is a match or the sequence has been repeated 25 times. The Flasherase Erase algorithm requires the device to be completely programmed prior to executing an erase command. To invoke the erase operation, the user writes an erase set-up command, an erase command, and an erase verify command. The user is required to time the erase pulse width in order to issue the erase verify command. An integrated stop timer prevents any possibility of overerasure. Upon completion of this sequence, the data is read back from the device and compared by the user with erased data. If there is not a match, the sequence is repeated until there is a match or the sequence has been repeated 1,000 times.
Embedded Erase Algorithm vs. Flasherase Erase Algorithm
AMD's Embedded Erase algorithm requires the user to only write an erase setup command and erase command. The device automatically pre-programs and verifies the entire array. The device then automatically times the erase pulse width, verifies the erase operation, and counts the number of sequences. A status bit, Data# Polling, provides the user with the erase operation status.
Commands are written to the command register using standard microprocessor write timings. Register cont e n t s serve as inputs to an internal state-machine which controls the erase and programming circuitry. Dur ing write cycles, the command register internally l a tc h e s address and data needed for the programming and erase operations. For system design simplification, the Am28F512A is designed to support either W E# or CE controlled writes. During a system write c ycl e, addresses are latched on the falling edge of WE# or CE# whichever occurs last. Data is latched on the rising edge of WE# or CE# whichever occurs first.
To simplify the following discussion, the WE# pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with respect to the WE# signal. AM D's Flash technology combines years of EPROM an d EEPROM experience to produce the highest leve ls of quality, reliability, and cost effectiveness. The A m 2 8 F 5 1 2 A electrically erases all bits simultane ously using Fowler-Nordheim tunneling. The bytes ar e programmed one byte at a time using the EPROM pr ogra mming mechanism of hot electron injection.
2
Am 2 8 F 5 1 2 A
BLOCK DIAGRAM
DQ0DQ7 VC C VSS VPP Erase Voltage Switch To Array WE# State Control Command Register CE# O E# Embedded Algorithms Y-Decoder Low VCC Detector Address Latch Program/Erase Pulse Timer Y-Gating Program Voltage Switch Chip Enable Output Enable Logic Input/Output Buffers
Data Latch
X-Decoder
524,288 Bit Cell Matrix
A0A15
18880C-1
PRODUCT SELECTOR GUIDE
Family Part Number Speed Options (VCC = 5.0 V ±10%) Max Access Time (ns) CE# (E#) Access (ns) OE# (G#) Access (ns) -70 70 70 35 -90 90 90 35 Am28F512A -120 120 120 50 -150 150 150 55 -200 200 200 55
Am28F512A
3
CONNECTION DIAGRAMS PDIP
VPP NC A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE# (W#) NC A14 A13 A8 A9 A11 OE# (G#) A10 CE# (E#) DQ7 DQ6 DQ5 DQ4 DQ3
18880C-2
PLCC
WE# (W#) NC VCC A 12 A 15 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DQ3 DQ5 DQ6 DQ1 DQ2 VSS DQ4 VPP NC
432
1 32 31 30 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE# (G#) A10 CE (E#) DQ7
18880C-3
Note: Pin 1 is marked for orientation.
4
Am 2 8 F 5 1 2 A
CONNECTION DIAGRAMS (Continued)
A11 A9 A8 A13 A14 NC W E# V CC VPP NC A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CE# D7 D6 D5 D4 D3 VSS D2 D1 D0 A0 A1 A2 A3
32-Pin TSOP--Standard Pinout
OE# A10 CE# D7 D6 D5 D4 D3 V SS D2 D1 D0 A0 A1 A2 A3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A11 A9 A8 A13 A14 NC WE# V CC VPP NC A15 A12 A7 A6 A5 A4
18880C-4
32-Pin TSOP--Reverse Pinout
LOGIC SYMBOL
16 A0A15 DQ0DQ7 CE# (E#) OE# (G#) WE# (W#) 8
18880C-5
Am28F512A
5
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