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Part: AM79C30A
Category:
Power Management
-> Supervisory Circuits
Description: Digital Subscriber Controller ( DSC Circuit
Company: Advanced Micro Devices, Inc.
Datasheet: Download AM79C30A datasheet File size : 1108 kB
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Datasheet text preview:
FINAL
Am79C30A/32A
Digital Subscriber ControllerTM (DSCTM) Circuit
DISTINCTIVE CHARACTERISTICS
s Combines CCITT I.430 S/T-Interface Transceiver, D-Channel LAPD Processor, Audio s Processor (DSC device only), and IOM-2 Interface in a single chip s Special operating modes allow realization of CCITT I.430 power-compliant terminal equipment s S- or T-Interface Transceiver -- Level 1 Physical Layer Controller -- Suppor ts point-to-point, short and extended passive bus configurations -- Provides multiframe support s Certified protocol software support available s CMOS technology, TTL compatible s D-channel processing capability -- Flag generation/detection -- CRC generation/checking -- Zero insertion/deletion -- Four 2-byte address detectors -- 32-byte receive and 16-byte transmit FIFOs
BLOCK DIAGRAM
SBP/IOM-2 Interface CAP1 CAP 2 SBIN SCLK BC L/CH2STRB* SBIOUT SFS
HSW
A INA ARE F A INB EAR 1 EAR 2 LS 1 LS 2
Audio Interface
Main Audio Processor (MAP) (Am79C30A Only)
Per ipheral Port (PP)
S/T Line Interface Unit (LIU) D Channel B1
LOUT1 LOUT2 LIN 1 LIN 2
Bd Be Bf
Ba
B-channel Multiplexer (M UX)
B2 D-Channel Data Link Controller (DL C )
XTAL1 XTAL2 MCLK
Oscillator (O SC) Bb Bc
D Channel CS WR RD Microprocessor Interface (M UX) RESET
D7 D6 D5 D4 D3 D2 D1 D0 INT A2 Microprocessor Interface
A1 A0 09893H-1
This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Publi cation# 09893 Rev: H Amendment/0 Issue Date: December 1998
S/T Interface
DISTINCTIVE CHARACTERISTICS (continued)
s Audio processing capability (DSC circuit only) -- Registers for implementation of software-based speaker phone algorithms -- Dual audio inputs -- Ear piece and loudspeaker drivers -- Codec/filter with A/µ selection -- Programmable gain and equalization filters -- Programmable sidetone level -- Programmable DTMF, single tone, progress tone, and ringer tone generation -- Programmable on-chip microphone amplifier s Pin and software compatible with the Am79C32A ISDN Data Controller (IDCTM) Circuit. The Am79C32A is used in data-only applications.
GENERAL DESCRIPTION
The Am79C30A Digital Subscriber Controller (DSC) Circuit and Am79C32A ISDN Data Controller (IDC) Circuit, shown in the Block Diagram, allow the realization of highly-integrated Terminal Equipment for the ISDN. T h e Am79C30A/32A is fully compatible with the CCITT-I-series recommendations for the S and T reference points, ensuring that the user of the device may des ign TEs which conform to the international standards. The Am79C30A/32A provides a 192-Kbit/s full duplex digital path over four wires between the TE located on th e subscriber's premises and the NT or PABX linecar d. All physical layer functions and procedures are implemented in accordance with CCITT Recommendation I.430, including framing, synchronization, maint e n a n c e , and multiple ter m i n a l contention. Both point-to-point and point-to-multipoint configurations are suppor ted. The Am79C30A/32A processes the ISDN basic rate bit stream, which consists of B1 (64 Kbit/s), B2 (64 Kbit/s), and D (16 Kbit/s) channels. The B channels are routed to and from different sections of the Am79C30A/32A under software control. The D channel is partially processed by the DSC/IDC circuit and is passed to the microprocessor for further processing. The Main Audio Processor (MAP) uses Digital Signal Pr ocess ing (DSP) to implement a high performance c odec /f ilt er function. The MAP interface supports a loudspeaker, an earpiece, and two separate audio inputs. Programmable on-chip gain is provided to simplify use of low output level microphones. The user may alter frequency response and gain of the MAP receive and transmit paths. Tone generators are included to implement ringing, call progress, and DTMF signals. A Peripheral Port (PP) is provided to allow the B channels to be routed off-chip for processing by other per i p h e r a l s . This por t is configurable as either an industr y-s tandard IOM-2 port, or as a serial bus port (SBP). The TE design process is simplified by the availability of certified protocol software packages, which provide complete system solutions through OSI Layer 3.
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Am79C30A/32A Data Sheet
CONNECTION DIAGRAMS Top View
44-Pin PLCC ARE F EA R2 EA R1 AI NB AI NA AVSS HSW 40 39 38 37 36 35 Am79C30A 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 LIN1 42 LIN2 41 L S2 L S1 44
CAP 1 CAP 2 AVCC DV CC RES ET CS RD WR DV SS A2 A1
7 8 9 10 11 12 13 14 15 16 17
43
6
5
4
3
2
1
LOUT1 LOUT2 AVSS DV SS INT XTAL1 XTAL2 MCLK SFS SCLK SBO UT
BCL/CH2STRB
44-Pin PLCC RSRVD RSRVD RSRVD RSRVD RSRVD ARE F HSW 40 39 38 37 36 35 Am79C32A 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 LIN1 42 LIN2 41 LS2 LS1
44
RSRVD RSRVD AVCC DV CC RES ET CS RD WR DV SS A2 A1
7 8 9 10 11 12 13 14 15 16 17
43
6
5
4
3
2
1
SBIN
A0
D7
D6
D5
D4
D3
D2
D1
D0
LOUT1 LOUT2 AVSS DV SS INT XTAL1 XTAL2 MCLK SFS SCLK SBO UT
BCL/CH2STR B
Note: 1. Pin 1 is marked for orientation purposes.
2. RSRVD = Reserved pin; should not be connected externally to any signal or supply.
Am79C30A/32A Data Sheet
SBIN
A0
D7
D6
D5
D4
D3
D2
D1
D0
3
CONNECTION DIAGRAMS (continued) Top View
44-Pin TQFP ARE F EA R2 EA R1 AI NB AI NA AVSS HSW 34 LIN1 36 LIN2 35 L S2 39 L S1 38
44
43
42
41
40
CAP 1 CAP 2 AVCC DV CC RES ET CS RD WR DV SS A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Am79C30A
37
33 32 31 30 29 28 27 26 25 24 23
LOUT1 LOUT2 AVSS DVSS I NT XTAL1 XTAL2 M CL K SFS SCLK SBOUT
BCL/CH2STRB
44-Pin TQFP RSRVD RSRVD RSRVD RSRVD RSRVD RSRVD HSW 34 33 32 31 30 29 Am79C32A 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 LIN1 36 LIN2 35 LS2 LS1
44
43
42
41
40
39
38
RSRVD RSRVD AVCC DV CC RES ET CS RD WR DV SS A2 A1
37
SBIN
A0
D7
D6
D5
D4
D3
D2
D1
D0
1 2 3 4 5 6 7 8 9 10 11
LOUT1 LOUT2 AVSS DVSS I NT XTAL1 XTAL2 M CL K SFS SCLK SBOUT
BCL/CH2STR B
Note: Pin 1 is marked for orientation purposes.
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Am79C30A/32A Data Sheet
SB IN
A0
D7
D6
D5
D4
D3
D2
D1
D0
ORDERING INFORMATION Standard Products
AMD ® standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.
AM79C30A/32A
J
C
OPTIONAL PROCESSING Blank = Standard Processing
TEM PERATURE RANGE C = Commercial (0°C to +70°C)
PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044) V = 44-Pin Thin Plastic Quad Flat Pack (PQT044)
SPEED OPTION Not Applicable DEVICE NAME/DESCRIPTION Am79C30A/32A Digital Subscriber Controller (DSC) device ISDN Data Controller (IDC) device
Valid Combinations AM79C30A AM79C32A JC, VC JC, VC
Valid Combinations Val id Combinations list configurations planned to be suppor ted in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Reference Appendix C, Figures 1 & 2, for specific mechanical dimensions of the two packages.
Am79C30A/32A Data Sheet
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