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Part: Am41PDS3228DT11I
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Description:
Company: Advanced Micro Devices, Inc.
Datasheet: Download Am41PDS3228DT11I datasheet File size : 791 kB
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PRELIMINARY
Am41PDS3228D
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29PDS322D 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Page Mode Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS MCP Features
Power supply voltage of 1.8 to 2.2 volt High performance
-- Access time as fast as 100 ns flash, 70 ns SRAM -- -- -- -- 24 mA active read current at 10 MHz for initial page read 0.5 mA active read current at 10 MHz for intra-page read 1 mA active read current at 20 MHz for intra-page read 200 nA in standby or automatic sleep mode
Package
-- 73-Ball FBGA
Minimum 1 million write cycles guaranteed per sector 20 year data retention at 125°C
-- Reliable operation for the life of the system
Operating Temperature
-- 40°C to +85°C
SOFTW ARE FEATURES
Data Management Software (DMS)
-- AMD-supplied software manages data programming, enabling EEPROM emulation -- Eases historical sector erase flash limitations
Flash Memory Features
ARCHIT ECTURAL ADVANTAGES
Simultaneous Read/Write operations
-- Data can be continuously read from one bank while executing erase/program functions in other bank. -- Zero latency between read and write operations
Erase Suspend/Erase Resume Data# Polling and Toggle Bits Unlock Bypass Program command
-- Reduces overall programming time when issuing multiple program command sequences
Page Mode Operation
-- 4 word page allows fast asynchronous reads
Dual Bank architecture
-- One 4 Mbit bank and one 28 Mbit bank
HARDWARE FEATURES
Any combination of sectors can be erased Ready/Busy# output (RY/BY#) Hardware reset pin (RESET#) WP#/ACC input pin
-- Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status -- Acceleration (ACC) function accelerates program timing
SecSi (Secured Silicon) Sector: Extra 64 KByte sector
-- Factory locked and identifiable: 16 byte Electronic Serial Number available for factory secure, random ID; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data -- Customer lockable: Can be read, programmed, or erased just like other sectors. Once locked, data cannot be changed
Sector protection
-- Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector -- Temporary Sector Unprotect allows changing data in protected sectors in-system
Zero Power Operation
-- Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero.
Top or bottom boot block Manufactured on 0.23 µm process technology Compatible with JEDEC standards
-- Pinout and software compatible with single-power-supply flash standard
SRAM Features
Power dissipation
-- Operating: 2 mA typical -- Standby: 0.5 µA typical
PERFORMANCE CHARACTERISTICS
High performance
-- Random access time of 100 ns at 1.8 V to 2.2 V VC C
Ultra low power consumption (typical values)
-- 2.5 mA active read current at 1 MHz for initial page read
CE1s# and CE2s Chip Select Power down features using CE1s# and CE2s Data retention supply voltage: 1.0 to 2.2 volt Byte data control: LB#s (DQ7DQ0), UB#s (DQ15DQ8)
This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed produc t without notice.
Publication# 26104 Rev: A Amendment/+1 Issue Date: May 13, 2002
Refer to AMD's Website (www.amd.com) for the latest information.
PRELIMINARY
GENERAL DESCRIPTION
T h e Am29PDS322D is a 32 Mbit, 1.8 V-only Flash m e m o r y organized as 2,097,152 words of 16 bits e a c h . The device is designed to be programmed in s ys tem with standard system 1.8 V VCC supply. This d e v i c e ca n a l s o be re p r o g r a m m e d in stand a r d EPROM programmers. The Am29PDS322D offers fast page access time of 40 ns with random access time of 100 ns (at 1.8 V to 2.2 V VCC), allowing operation of high-speed microproces sors without wait states. To eliminate bus contenti on the device has separate chip enable (CE), write e na b le (WE), and output enable (OE) controls. The page size is 4 words. The device requires only a single 1.8 volt power supp l y for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. other flash sector, or may permanently lock their own code there. DM S (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all fu nctio ns necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs t o state which piece of data is to be updated, and where the updated data is located in the system. This i s a n a d v a n t a g e c o m p a r e d to sy s t e m s w h e r e us er-written software must keep track of the old data loc ati on, status, logical to physical translation of the dat a onto the Flash memory device (or memory devi ce s), and more. Using DMS, user-written software does not need to interface with the Flash memory directly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD provides this software to simplify system design and software integration efforts. The device offers complete compatibility with the JE DE C single-power-supply Flash command set s ta n da r d . Commands are written to the command register using standard microprocessor write timings. Re ad in g data out of the device is similar to reading from other Flash or EPROM devices. Th e host system can detect whether a program or erase operation is complete by using the device stat u s bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to the read mode. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Har dwar e data protection measures include a low V CC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of tim e, the device enters the automatic sleep mode. T h e system can also place the de v i c e into the s t a n d b y mode. Power consumption is greatly reduced in both modes.
Simultaneous Read/Write Operations with Zero Latency
Th e Simultaneous Read/Write architecture provides s i m u l t a n e o u s operation by dividing the memory space into two banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and sim u l t a n e o u s l y read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The device is divided as shown in the following table:
Bank 1 Sectors Q u a n ti ty 8 7 Size 4 Kwords 56 32 Kwords 4 Mbits total 28 Mbits total 32 Kwords Bank 2 Sectors Q u a n ti ty Size
Am29PDS322D Features
T h e SecSi (Secured Silicon) Sector is an extra 64 KByte sector capable of being permanently locked by AMD or customers. The SecSi Indicator Bit (DQ7) is p erma nen tly set to a 1 if the part is factory locked, a nd set to a 0 if customer lockable. This way, custome r lockable parts can never be used to replace a factory locked part. F a c t o r y locked parts provide several options. The S e c S i Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (prog ra mm e d through AMD's ExpressFlash service), or both. Customer Lockable parts may utilize the SecSi S ec tor as bonus space, reading and writing like any
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Am41PDS3228D
May 13, 2002
PRELIMINARY
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5 Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7 Special Package Handling Instructions ... 7 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9 MCP Device Bus Operations. . . . . . . . . . . . . . . . 10
Table 1. Device Bus Operations--SRAM Word Mode, CIOs = VCC 10 Table 2. Device Bus Operations--SRAM Byte Mode, CIOs = VSS 11
Chip Erase Command Sequence .......... 24 Sector Erase Command Sequence ....... 25 Erase Suspend/Erase Resume Commands ... 25
Figure 5. Erase Operation..... 26 Table 10. Am29PDS322D Command Definitions ... 27
Flash Write Operation Status . . . . . . . . . . . . . . . 28 DQ7: Data# Polling ........ 28
Figure 6. Data# Polling Algorithm ........ 28
RY/BY#: Ready/Busy# ... 29 DQ6: Toggle Bit I ........... 29
Figure 7. Toggle Bit Algorithm........ 29
Flash Device Bus Operations . . . . . . . . . . . . . . . 12 Requirements for Reading Array Data .. 12 Read Mode ........... 12 Random Read (Non-Page Mode Read) ...... 12 Page Mode Read ........... 12
Table 3. Page Word Mode .....12
DQ2: Toggle Bit II .......... 30 Reading Toggle Bits DQ6/DQ2 ..... 30 DQ5: Exceeded Timing Limits ...... 30 DQ3: Sector Erase Timer ....... 30
Table 11. Write Operation Status ......... 31
Writing Commands/Command Sequences .... 12 Accelerated Program Operation ......... 12 Autoselect Functions .. 13 Simultaneous Read/Write Operations with Zero Latency ....... 13 Standby Mode ...... 13 Automatic Sleep Mode .. 13 RESET#: Hardware Reset Pin ..... 13 Output Disable Mode ..... 14
Table 4. Am29PDS322DT Top Boot Sector Addresses .........14 Table 5. Am29PDS322DT Top Boot SecSi Sector Address ..15 Table 6. Am29PDS322DB Bottom Boot Sector Addresses ...15 Am29PDS322DB Bottom Boot SecSi Sector Address........... 17
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 32 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 32 Industrial (I) Devices ... 32 VCCf/VCC s Supply Voltage ......... 32 Flash DC Characteristics . . . . . . . . . . . . . . . . . . 33 CMOS Compatible ......... 33 SRAM DC and Operating Characteristics . . . . . 34
Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ...... 35 Figure 11. Typical ICC1 vs. Frequency ........... 35
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 12. Test Setup........... 36 Table 12. Test Specifications ......... 36
Autoselect Mode ............ 17 Sector/Sector Block Protection and Unprotection ......... 17
Table 8. Top Boot Sector/Sector Block Addresses for Protection/Unprotection .......17 Table 9. Bottom Boot Sector/Sector Block Addresses for Protection/Unprotection ...........18
Key To Switching Waveforms . . . . . . . . . . . . . . . 36
Figure 13. Input Waveforms and Measurement Levels ........ 36
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37 SRAM CE#s Timing ....... 37
Figure 14. Timing Diagram for Alternating Between SRAM to Flash ....... 37 Figure 15. Conventional Read Operation Timings ....... 38 Figure 16. Page Mode Read Timings ........... 39
Write Protect (WP#) ....... 18 Temporary Sector/Sector Block Unprotect ..... 18
Figure 1. Temporary Sector Unprotect Operation... 19 Figure 2. In-System Sector/Sector Block Protect and Unprotect Algorithms .... 20
Hardware Reset (RESET#) .... 40
Figure 17. Reset Timings ...... 40
Flash Erase and Program Operations ... 41
Figure 18. Program Operation Timings......... Figure 19. Accelerated Program Timing Diagram.. Figure 20. Chip/Sector Erase Operation Timings .. Figure 21. Back-to-back Read/Write Cycle Timings .... Figure 22. Data# Polling Timings (During Embedded Algorithms). Figure 23. Toggle Bit Timings (During Embedded Algorithms)...... Figure 24. DQ2 vs. DQ6........ 42 42 43 44 44 45 45
SecSi (Secured Silicon) Sector Flash Memory Region .......... 21 Factory Locked: SecSi Sector Programmed and Protected at the Factory .... 21 Hardware Data Protection ...... 21 Low VCC Write Inhibit .. 21 Write Pulse "Glitch" Protection ........... 22 Logical Inhibit .... 22 Power-Up Write Inhibit ......... 22 Flash Command Definitions . . . . . . . . . . . . . . . . 22 Reading Array Data ....... 22 Reset Command ............ 22 Autoselect Command Sequence ........... 22 Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 23 Word Program Command Sequence .... 23 Unlock Bypass Command Sequence .......... 23
Figure 3. Unlock Bypass Algorithm ....... 24 Figure 4. Program Operation .......... 24
Temporary Sector/Sector Block Unprotect ..... 46
Figure 25. Temporary Sector/Sector Block Unprotect Timing Diagram...... 46 Figure 26. Sector/Sector Block Protect and Unprotect Timing Diagram...... 47
Alternate CE#f Controlled Erase and Program Operations .... 48
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings....... 49
SRAM AC Characteristics . . . . . . . . . . . . . . . . . . 50 Read Cycle ........... 50
Figure 28. SRAM Read Cycle--Address Controlled.... 50 Figure 29. SRAM Read Cycle ........ 51
May 13, 2002
Am41PDS3228D
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PRELIMINARY Write Cycle ........... 52
Figure 30. SRAM Write Cycle--WE# Control ......... 52 Figure 31. SRAM Write Cycle--CE1#s Control ...... 53 Figure 32. SRAM Write Cycle--UB#s and LB#s Control ....... 54
SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 56
Figure 33. CE1#s Controlled Data Retention Mode..... 56 Figure 34. CE2s Controlled Data Retention Mode....... 56
Flash Erase And Programming Performance . . 55 Flash Latchup Characteristics . . . . . . . . . . . . . . 55 Package Pin Capacitance . . . . . . . . . . . . . . . . . . 55 Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 55
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 57 FLB073--73-Ball Fine-Pitch Grid Array 8 x 11.6 mm .... 57 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 58 Revision A (February 21, 2002) .... 58 Revision A+1 (May 13, 2002) ....... 58
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Am41PDS3228D
May 13, 2002
PRELIMINARY
PRODUCT SELECTOR GUIDE
Part Number Speed Options Standard Voltage Range: VCC = 1.82.2 V Am41PDS3228D Flash Memory 10 100 100 35 40 11 110 110 40 45 SRAM 10, 11 70 70 35 N /A
Max Access Time (ns) CE# Access (ns) OE# Access (ns) Max Page Address Access Time (ns)
MCP BLOCK DIAGRAM
VCCf VSS RY/BY#
A20 to A0 WP#/ACC RESET# CE#f
A20 to A0
32 M Bit Flash Memory DQ15 to DQ0
DQ15 to DQ0 VCCs/VCCQ VSS/VSSQ
A0 8 to A0 A1 to A19 SA LB#s UB#s WE# OE# CE1#s CE2s CIOs 8 M Bit Static RAM
DQ15 to DQ0
May 13, 2002
Am41PDS3228D
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