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Part: AM29SL160CT-150
Category:
Memory
-> Flash
-> 16 Mb
Description:
Company: Advanced Micro Devices, Inc.
Datasheet: Download AM29SL160CT-150 datasheet File size : 1162 kB
Request For quote: Find where to buy AM29SL160CT-150
Datasheet text preview:
Am29SL160C
16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES Secured Silicon (SecSi) Sector: 256-byte sector -- Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data -- Customer lockable: Customer may program own custom data. Once locked, data cannot be changed Zero Power Operation -- Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero Package options -- 48-ball FBGA -- 48-pin TSOP Top or bottom boot block Manufactured on 0.32 µm process technology Compatible with JEDEC standards -- Pinout and software compatible with single-powersupply flash standard PERFORMANCE CHARACTERISTICS High performance -- Access time as fast 90 ns -- Program time: 8 µs/word typical using Accelerate Ultra low power consumption (typical values) -- 1 mA active read current at 1 MHz -- 5 mA active read current at 5 MHz -- 1 µA in standby or automatic sleep mode Minimum 1 million erase cycles guaranteed per sector 20 Year data retention at 125°C -- Reliable operation for the life of the system SOFTWARE FEATURES Supports Common Flash Memory Interface (CFI) Erase Suspend/Erase Resume -- Suspends erase operations to allow programming in same bank Data# Polling and Toggle Bits -- Provides a software method of detecting the status of program or erase cycles Unlock Bypass Program command -- Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES Any combination of sectors can be erased Ready/Busy# output (RY/BY#) -- Hardware method for detecting program or erase cycle completion Hardware reset pin (RESET#) -- Hardware method of resetting the internal state machine to reading array data WP#/ACC input pin -- Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status -- Acceleration (ACC) function accelerates program timing Sector protection -- Hardware method of locking a sector, either insystem or using programming equipment, to prevent any program or erase operation within that sector -- Temporary Sector Unprotect allows changing data in protected sectors in-system
This Data Sheet states AMD's current specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 21635 R ev: C Am endment/ +2 Issue Date: June 11, 2002
Refer to AMD's Website (www amd com) for the latest information
GENERAL DESCRIPTION
The Am29SL160C is a 16 Mbit, 1.8 V volt-only Flash memory organized as 2,097,152 bytes or 1,048,576 words. The data appears on DQ0DQ15. The device is offered in 48-pin TSOP and 48-ball FBGA packages. The word-wide data (x16) appears on DQ15DQ0; the byte-wide (x8) data appears on DQ7DQ0. This device is designed to be programmed and erased in-system with a single 1.8 volt VCC supply. No VPP is required for program or erase operations. The device can also be programmed in standard EPROM programmers. The standard device offers access times of 90, 100, 120, or 150 ns, allowing microprocessors to operate wit hout wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. T h e device requires only a single 1.8 volt power sup p ly for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Comm a n d s are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program c om m a nd sequence. This initiates the Embedded Program algorithm--an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. D e v i c e erasure occurs by executing the erase c om m a nd sequence. This initiates the Embedded Erase algorithm--an internal algorithm that automatic a l l y preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the d a t a contents of other sectors. The device is fully erased when shipped from the factory. Hardw are data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector prot e c t i o n feature disables both program and erase o p e r a t i o n s in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. T he device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both m o d e s. A M D's Flash technology combines years of Flash m e m o r y manufacturing experience to produce the highest levels of quality, reliability and cost effectiven e s s . The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.
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Am29SL160C
June 11, 2002
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5 Special Handling Instructions for FBGA Packages ......... 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Am29SL160C Device Bus Operations .......9 Table 12. Am29SL160C Command Definitions ..... 26
Write Operation Status . . . . . . . . . . . . . . . . . . . . 27 DQ7: Data# Polling ........ 27
Figure 5. Data# Polling Algorithm ........ 27
Word/Byte Configuration .......... 9 Requirements for Reading Array Data .... 9 Writing Commands/Command Sequences .... 10 Accelerated Program Operation ............ 10 Program and Erase Operation Status ... 10 Standby Mode ...... 10 Automatic Sleep Mode .. 10 RESET#: Hardware Reset Pin ..... 10 Output Disable Mode ..... 11
Table 2. Am29SL160CT Top Boot Sector Architecture .........12 Table 3. Am29SL160CB Bottom Boot Sector Architecture ....13
RY/BY#: Ready/Busy# ... 28 DQ6: Toggle Bit I ........... 28 DQ2: Toggle Bit II .......... 28 Reading Toggle Bits DQ6/DQ2 ..... 28 DQ5: Exceeded Timing Limits ...... 29 DQ3: Sector Erase Timer ....... 29
Figure 6. Toggle Bit Algorithm........ 29 Table 13. Write Operation Status ......... 30
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 31
Figure 7. Maximum Negative Overshoot Waveform .... 31 Figure 8. Maximum Positive Overshoot Waveform ...... 31
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 31 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ...... 33 Figure 10. Typical ICC1 vs. Frequency ........... 33
Autoselect Mode ............ 14
Table 4. Am29SL160C Autoselect Codes (High Voltage Method) ..14
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 11. Test Setup............ 34 Table 14. Test Specifications ......... 34 Figure 12. Input Waveforms and Measurement Levels ........ 34
Sector/Sector Block Protection and Unprotection ......... 15
Table 5. Top Boot Sector/Sector Block Addresses for Protection/Unprotection ....15 Table 6. Bottom Boot Sector/Sector Block Addresses for Protection/Unprotection ..........15
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35 Read Operations ........... 35
Figure 13. Read Operations Timings ............ 35
Write Protect (WP#) ....... 16 Temporary Sector Unprotect ........ 16
Figure 1. In-System Sector Protect/Unprotect Algorithms ..... 17 Figure 2. Temporary Sector Unprotect Operation... 18
Hardware Reset (RESET#) .... 36
Figure 14. RESET# Timings .......... 36
Word/Byte Configuration (BYTE#) ....... 37
Figure 15. BYTE# Timings for Read Operations.... 37 Figure 16. BYTE# Timings for Write Operations.... 37
Secured Silicon (SecSi) Sector Flash Memory Region .......... 18
Table 7. SecSi Sector Addresses .........18
Erase/Program Operations ..... 38
Figure 17. Program Operation Timings......... Figure 18. Chip/Sector Erase Operation Timings .. Figure 19. Data# Polling Timings (During Embedded Algorithms). Figure 20. Toggle Bit Timings (During Embedded Algorithms)...... Figure 21. DQ2 vs. DQ6........ Figure 22. Temporary Sector Unprotect Timing Diagram ..... Figure 23. Accelerated Program Timing Diagram.. Figure 24. Sector Protect/Unprotect Timing Diagram ........... Figure 25. Alternate CE# Controlled Write Operation Timings ...... 39 40 41 41 42 42 43 43 45
Hardware Data Protection ...... 18 Low VCC Write Inhibit ..... 18 Write Pulse "Glitch" Protection ..... 18 Logical Inhibit ........ 18 Power-Up Write Inhibit ... 18 Common Flash Memory Interface (CFI) . . . . . . . 19
Table 8. CFI Query Identification String .........19 Table 9. System Interface String .....20 Table 10. Device Geometry Definition ...........20 Table 11. Primary Vendor-Specific Extended Query ....21
Command Definitions . . . . . . . . . . . . . . . . . . . . . 21 Reading Array Data ....... 21 Reset Command ............ 21 Autoselect Command Sequence ........... 22 Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 22 Word/Byte Program Command Sequence ..... 22 Unlock Bypass Command Sequence .... 22
Figure 3. Program Operation .......... 23
Chip Erase Command Sequence .......... 24 Sector Erase Command Sequence ....... 24 Erase Suspend/Erase Resume Commands ... 24
Figure 4. Erase Operation...... 25
Erase And Programming Performance . . . . . . . 46 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 46 TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 46 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Physical Dimensions* . . . . . . . . . . . . . . . . . . . . . 47 TS 048--48-Pin Standard TSOP ........... 47 FBC048--48-Ball Fine-Pitch Ball Grid Array (FBGA) 8 x 9 mm package ......... 48 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 49 Revision B (December 14, 1999) ........... 49 Revision C (February 21, 2000) .... 49 Revision C+1 (November 14, 2000) ...... 49 Revision C+2 (June 11, 2002) ...... 50
Command Definitions .... 26
June 11, 2002
Am29SL160C
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PRODUCT SELECTOR GUIDE
Family Part Number Speed Options Max access time, ns (tACC) Max CE# access time, ns (tCE) Max OE# access time, ns (tOE) Note:See "AC Characteristics" for full specifications. - 90 90 90 35 Am29SL160C -100 100 100 35 -120 12 0 12 0 50 - 150 150 150 65
BLOCK DIAGRAM
RY/BY#
VCC VSS Sector Switches Erase Voltage Generator Inp u t/O utp u t Buffers DQ0DQ15 (A-1)
RESET#
WE# BY TE# WP#/ACC
S ta te C ontr ol Command R e g i s te r
P GM Voltage Generator Chip Enable Output Enable Logic ST B Data L a tc h
CE# O E#
ST B V C C Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A 0 A 19
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Am29SL160C
June 11, 2002
CONNECTION DIAGRAMS
A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# RESET# NC WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Standard TSOP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
June 11, 2002
Am29SL160C
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