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Part: AM29LV641GH
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Company: Advanced Micro Devices, Inc.
Datasheet: Download AM29LV641GH datasheet File size : 1450 kB
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Am29LV640GH/L , Am29LV640GU
Data Sheet
July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.
Publication Number 25295 Revision A
Amendment +2 Issue Date October 18, 2002
ADVANCE INFORMATION
Am29LV641GH/L / Am29LV640GU
64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O Control
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
s Single power supply operation -- 2.7 to 3.6 volt read, erase, and program operations s SecSi (Secured Silicon) Sector region -- 128-word sector for permanent, secure identification through an 8-word random Electronic Serial Number -- May be programmed and locked at the factory or by the customer -- Accessible through a command sequence s VersatileI/O control -- Device generates data output voltages and tolerates data input voltages as determined by the voltage on the VIO pin s Manufactured on 0.18 µm process technology s Flexible sector architecture -- One hundred twenty-eight 32 Kword sectors s Compatibility with JEDEC standards -- Pinout and software compatible with single-power supply Flash standard s Package options -- 48-pin TSOP and Reverse TSOP (LV641GH/L only) -- 63-ball Fine-Pitch BGA (LV640GU only) -- 64-ball Fortified BGA (LV640GU only) s Minimum 1 million erase cycle guarantee per sector s 20-year data retention at 125°C s Ultra low power consumption (typical values at 3.0 V, 5 MHz) -- 9 mA typical active read current -- 26 mA typical erase/program current -- 200 nA typical standby mode current s Program and erase performance (VHH not applied to the ACC input pin) -- Word program time: 7 µs typical -- Sector erase time: 0.6 s typical for each 32 Kword sector
SOFTWARE AND HARDWARE FEATURES
s Hardware features -- Hardware reset input (RESET#): resets device for new operation -- WP# input: protects first or last 32 Kword sector regardless of sector protection settings (LV641GH/L only) -- ACC input: Accelerates programming time for higher throughput during system production s Software features -- Program Suspend & Resume: read other sectors before programming operation is completed -- Sector Group Protection: VCC-level method of preventing program or erase operations within a sector -- Temporary Sector Group Unprotect: VID-level method of changing in previously locked sectors -- CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices -- Erase Suspend/Erase Resume: read/program other sectors before an erase operation is complete -- Data# Polling and toggle bits provide erase and programming operation status -- Unlock Bypass Program command reduces overall multiple-word programming time
PERFORMANCE CHARCTERISTICS
s High performance -- Access time ratings as fast as 55 ns
This document contains information on a product under development at Advance Micro Devices. The information is intended to help you evaluate this product. Do not design in the product without contacting the factory. AMD reserves the right to change or discontinue work on this proposed product without notice.
Publication# 25295 Rev: A Amendment/+2 Issue Date: October 18, 2002
Refer to AMD's Website (www.amd.com) for the latest information.
ADVANCE
INFORMATION
GENERAL DESCRIPTION
The Am29LV641GH/L / Am29LV640GU are 64 Mbit, 3 . 0 volt (3.0 V to 3.6 V) single power supply flash memory devices organized as 4,194,304 words. Data appears on DQ15DQ0. These devices are designed to be programmed in-system with the standard system 3.0 volt VCC supply. A 12.0 volt VPP is not required for program or erase operations. The device can also be programmed in standard EPROM programmers. A cc e s s times of 55 regulated volage and 70 ns full voltage range are available for applications where VIO V C C . The Am29LV641GH/L is offered in 48-pin TSOP and reverse TSOP packages. The Am29LV640GU is offered in a 63-ball Fine-pitch BGA package, and a 64-ball Fortified BGA. To eliminate bus c o n t e n t i o n each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. E a ch device requires only a single 3.0 volt power supply (2.7 V to 3.6 V) for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with t h e JEDEC single-power-supply Flash standard. Commands are written to the command register using sta n da rd microprocessor write timing. Register contents serve as inputs to an internal state-machine that c o n tr o l s the erase and programming circuitry. Write c y c l e s also internally latch addresses and data n e e d e d for the programming and erase operations. R e a d in g data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program c o m m a n d sequence. This initiates the Embedded Program algorithm--an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. D e vice erasure occurs by executing the erase command sequence. This initiates the Embedded Erase a l g o ri t h m -- a n internal algorithm that automatically p r e p r o g r a m s the array (if it is not already programmed) before executing the erase operation. Duri n g erase, the device automatically times the erase pulse widths and verifies proper cell margin. The VersatileI/OTM (VIO) control allows the host system to set the voltage levels that the device generates a t its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the VIO pin. This allows the device to operate in 1.8 V or 3 V system environment as required. T h e host system can detect whether a program or e r a s e operation is complete by reading the DQ7 ( D a t a# Polling) or DQ6 (toggle) status bits. After a program or erase cycle has been completed, the de2 v i c e is ready to read array data or accept another c ommand. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. H ar dware data protection measures include a low V C C detector that automatically inhibits write operat io n s during power transitions. The hardware sector p r o te ct io n feature disables both program and erase operations in any combination of sectors of memory. Th is can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thu s be achieved. The Program Suspend/Program Resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to r e ad in g array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read boot-up firmware from the Flash memory device. The device offers a standby mode as a power-saving fe a ture . Once the system places the device into the standby mode power consumption is greatly reduced. T he SecSi (Secured Silicon) Sector provides an minimum 128-word area for code or data that can be permanently protected. Once this sector is protected, n o further programming or erasing within the sector can occur. The Write Protect (WP#) feature protects the first or l a st sector by asserting a logic low on the WP# pin. The protected sector will still be protected even during accelerated programming. (Am29LV641GH/L only) The accelerated program (ACC) feature allows the system to program the device at a much faster rate. When ACC is pulled high to VHH, the device enters the Unlock Bypass mode, enabling the user to reduce the time needed to do the program operation. This feature is intended to increase factory throughput during system production, but may also be used in the field if desired. A M D 's Flash technology combines years of Flash m e m o r y manufacturing experience to produce the highest levels of quality, reliability and cost effectiven e ss. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunnelling. The data is programmed using hot electron injection. October 18, 2002
Am29LV641GH/L / Am29LV640GU
ADVANCE
INFORMATION
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5 Special Package Handling Instructions ... 7 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10 VersatileI/O (VIO) Control .... 10 Requirements for Reading Array Data .. 10 Writing Commands/Command Sequences .... 11
Table 1. Device Bus Operations .....10
DQ7: Data# Polling ........ 30
Figure 6. Data# Polling Algorithm ........ 30
DQ6: Toggle Bit I ........... 30
Figure 7. Toggle Bit Algorithm........ 31
DQ2: Toggle Bit II .......... 32 Reading Toggle Bits DQ6/DQ2 ..... 32 DQ5: Exceeded Timing Limits ...... 32 DQ3: Sector Erase Timer ....... 32
Table 11. Write Operation Status ......... 33
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 34
Figure 8. Maximum Negative Overshoot Waveform ............ 34 Figure 9. Maximum Positive Overshoot Waveform ..... 34
Accelerated Program Operation ......11 Autoselect Functions .....11
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 34 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) .......... 36 Figure 11. Typical ICC1 vs. Frequency ........... 36
Standby Mode ...... 11 Automatic Sleep Mode .. 11 RESET#: Hardware Reset Pin ..... 11 Output Disable Mode ..... 12
Table 2. Sector Address Table ........12
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 12. Test Setup........... 37 Table 12. Test Specifications ......... 37
Autoselect Mode ............ 16
Table 3. Autoselect Codes, (High Voltage Method) ....16
Key to Switching Waveforms. . . . . . . . . . . . . . . . 37
Figure 13. Input Waveforms and Measurement Levels.... 37
Sector Group Protection and Unprotection ..... 17
Table 4. Sector Group Protection/Unprotection Address Table .....17
Write Protect (WP#) ....... 18 Temporary Sector Group Unprotect ...... 18 SecSi (Secured Silicon) Sector Flash Memory Region ....... 20
Table 5. SecSi Sector Contents ......20 Figure 3. SecSi Sector Protect Verify.... 21 Figure 1. Temporary Sector Group Unprotect Operation ....... 18 Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 19
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38 Read-Only Operations .. 38
Figure 14. Read Operation Timings ..... 38
Hardware Reset (RESET#) .... 39
Figure 15. Reset Timings ...... 39
Erase and Program Operations .... 40
Figure 16. Program Operation Timings......... Figure 17. Accelerated Program Timing Diagram.. Figure 18. Chip/Sector Erase Operation Timings .. Figure 19. Data# Polling Timings (During Embedded Algorithms)...... Figure 20. Toggle Bit Timings (During Embedded Algorithms)...... Figure 21. DQ2 vs. DQ6........ 41 41 42 43 44 44
Hardware Data Protection ...... 21
Low VCC Write Inhibit .....21 Write Pulse "Glitch" Protection ........21 Logical Inhibit ..........21 Power-Up Write Inhibit ...........21
Common Flash Memory Interface (CFI) . . . . . . . 21
Table 6. CFI Query Identification String ......... 22 Table 7. System Interface String..... 22 Table 8. Device Geometry Definition .... 22 Table 9. Primary Vendor-Specific Extended Query ...... 24
Temporary Sector Unprotect ........ 45
Figure 22. Temporary Sector Group Unprotect Timing Diagram ... 45 Figure 23. Sector Group Protect and Unprotect Timing Diagram .. 46
Command Definitions . . . . . . . . . . . . . . . . . . . . . 24 Reading Array Data ....... 24 Reset Command ............ 25 Autoselect Command Sequence ........... 25 Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 25 Word Program Command Sequence .... 25
Unlock Bypass Command Sequence ....26 Figure 4. Program Operation .......... 26
Alternate CE# Controlled Erase and Program Operations ..... 47
Figure 24. Alternate CE# Controlled Write (Erase/Program) Operation Timings .... 48
Chip Erase Command Sequence .......... 26 Sector Erase Command Sequence ....... 27 Erase Suspend/Erase Resume Commands ... 27
Figure 5. Erase Operation...... 28
Command Definitions .... 29
Table 10. Command Definitions...... 29
Erase And Programming Performance . . . . . . . 49 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 49 TSOP & FBGA Pin Capacitance. . . . . . . . . . . . . . 49 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 FBE063--63-Ball Fine-Pitch Ball Grid Array (FBGA) 11 x 12 mm package ....... 50 LAA06464-Ball Fortified Ball Grid Array (Fortified BGA) 13 x 11 mm package ......... 51 TS 048--48-Pin Standard TSOP ........... 52 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 53
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 30
October 18, 2002
Am29LV641GH/L / Am29LV640GU
3
ADVANCE
INFORMATION
PRODUCT SELECTOR GUIDE
Part Number Speed Option Max Access Time (ns) CE# Access Time (ns) OE# Access Time (ns) Note: See "AC Characteristics" for full specifications. Regulated Voltage Range VCC = 3.03.6 V Standard Voltage Range VCC = 2.73.6 V 55 55 35 Am29LV641GH/L / Am29LV640GU 55R 70 70 70 35
BLOCK DIAGRAM
DQ15DQ0 VCC VSS RESET# Erase Voltage Generator VIO Input/Output Buffers Sector Switches
WE# WP# A CC RY/BY#
State Co ntro l Command Register
PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE # OE#
STB VCC Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A21A0
4
Am29LV641GH/L / Am29LV640GU
October 18, 2002
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