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Part: AM29LV200BT55R
Category:
Memory
-> Flash
-> 2 Mb
Description:
Company: Advanced Micro Devices, Inc.
Datasheet: Download AM29LV200BT55R datasheet File size : 1747 kB
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Datasheet text preview:
Am29LV200B
2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s Single power supply operation -- 2.7 to 3.6 volt read and write operations for battery-powered applications s Manufactured on 0.32 µm process technology -- Compatible with 0.5 µm Am29LV200 device s High performance -- Full voltage range: access times as fast as 70 ns -- Regulated voltage range: access times as fast as 55 ns s Ultra low power consumption (typical values at 5 MHz) -- 200 nA Automatic Sleep mode current -- 200 nA standby mode current -- 7 mA read current -- 15 mA program/erase current s Flexible sector architecture -- One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and three 64 Kbyte sectors (byte mode) -- One 8 Kword, two 4 Kword, one 16 Kword, and three 32 Kword sectors (word mode) -- Supports full chip erase -- Sector Protection features: A hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked in-system or via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors s Unlock Bypass Program Command -- Reduces overall programming time when issuing multiple program command sequences s Top or bottom boot block configurations available s Embedded Algorithms -- Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors -- Embedded Program algorithm automatically writes and verifies data at specified addresses s Minimum 1 million erase cycle guarantee per sector s 20-year data retention at 125°C -- Reliable operation for the life of the system s Package option -- 48-pin TSOP -- 44-pin SO -- 48-ball FBGA s Compatibility with JEDEC standards -- Pinout and software compatible with singlepower supply Flash -- Superior inadvertent write protection s Data# Polling and toggle bits -- Provides a software method of detecting program or erase operation completion s Ready/Busy# pin (RY/BY#) -- Provides a hardware method of detecting program or erase cycle completion s Erase Suspend/Erase Resume -- Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation s Hardware reset pin (RESET#) -- Hardware method to reset the device to reading array data
This Data Sheet states AMD's current technical specifications regarding the Products described herein. This Data Shee t may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 21521 R ev: D Am endment/ +2 Issue Date: April 12, 2002
GENERAL DESCRIPTION
T h e Am29LV200B is a 2 Mbit, 3.0 volt-only Flash memory organized as 262,144 bytes or 131,072 words. The device is offered in 44-pin SO, 48-pin TSOP, and 48-ba ll FBGA packages. The word-wide data (x16) appears on DQ15-DQ0; the byte-wide (x8) data appears o n DQ7-DQ0. This device is designed to be programmed in-system using only a single 3.0 volt VC C supply. No VPP is required for write or erase operations. T h e device can also be programmed in standard EPROM programmers. T his device is manufactured using AMD's 0.32 µm proc ess technology, and offers all the features and benefits of the Am29LV200, which was manufactured us in g 0.5 µm process technology. In addition, the Am29LV200B features unlock bypass programming and in-system sector protection/unprotection. The standard device offers access times of 55, 70, 90 and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. T h e device requires only a single 3.0 volt power sup p ly for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Comm a n d s are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program c om m a nd sequence. This initiates the Embedded Program algorithm--an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. D e v i c e erasure occurs by executing the erase c om m a nd sequence. This initiates the Embedded Erase algorithm--an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the d a t a contents of other sectors. The device is fully erased when shipped from the factory. Hardw are data protection measures include a low V C C detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase o p e r a t i o n s in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. T he device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. A M D's Flash technology combines years of Flash m e m o r y manufacturing experience to produce the highest levels of quality, reliability and cost effectiven e s s . The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.
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Am29LV200B
April 12, 2002
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5 Special Handling Instructions ......... 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Am29LV200B Device Bus Operations ........ 9
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 24 Extended (E) Devices .... 24 VCC Supply Voltages ..... 24 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ...... 26 Figure 10. Typical ICC1 vs. Frequency .......... 26
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 11. Test Setup ............ 27 Table 7. Test Specifications .. 27
Word/Byte Configuration .......... 9 Requirements for Reading Array Data .... 9 Writing Commands/Command Sequences ...... 9 Program and Erase Operation Status ... 10 Standby Mode ...... 10 Automatic Sleep Mode .......10 RESET#: Hardware Reset Pin .........10 Output Disable Mode ..... 11
Table 2. Am29LV200BT Top Boot Block Sector Address Table..... 11 Table 3. Am29LV200BB Bottom Boot Block Sector Address Table 11
Key to Switching Waveforms. . . . . . . . . . . . . . . . 27
Figure 12. Input Waveforms and Measurement Levels ........ 27
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28 Read Operations ........... 28
Figure 13. Read Operations Timings ............ 28
Hardware Reset (RESET#) .... 29
Figure 14. RESET# Timings .......... 29
Word/Byte Configuration (BYTE#) ....... 30
Figure 15. BYTE# Timings for Read Operations .... 30 Figure 16. BYTE# Timings for Write Operations .... 30
Autoselect Mode ............ 11
Table 4. Am29LV200B Autoselect Codes (High Voltage Method).. 12
Erase/Program Operations ..... 31
Figure 17. Program Operation Timings ......... 32 Figure 18. Chip/Sector Erase Operation Timings .. 33 Figure 19. Data# Polling Timings (During Embedded Algorithms) . 34 Figure 20. Toggle Bit Timings (During Embedded Algorithms) ...... 34 Figure 21. DQ2 vs. DQ6 ........ 35
Sector Protection/Unprotection ..... 12 Temporary Sector Unprotect ........ 12
Figure 1. In-System Sector Protect/Unprotect Algorithms ......13 Figure 2. Temporary Sector Unprotect Operation ...14
Hardware Data Protection ...... 14 Low VCC Write Inhibit ..... 14 Write Pulse "Glitch" Protection ..... 14 Logical Inhibit ........ 14 Power-Up Write Inhibit ... 14 Command Definitions . . . . . . . . . . . . . . . . . . . . . . 15 Reading Array Data ....... 15 Reset Command ............ 15 Autoselect Command Sequence ........... 15 Word/Byte Program Command Sequence ..... 15 Unlock Bypass Command Sequence .... 16
Figure 3. Program Operation ..........16
Temporary Sector Unprotect ........ 35
Figure 22. Temporary Sector Unprotect Timing Diagram ..... 35 Figure 23. Sector Protect/Unprotect Timing Diagram ........... 36
Alternate CE# Controlled Erase/Program Operations ... 37
Figure 24. Alternate CE# Controlled Write Operation Timings ...... 38
Chip Erase Command Sequence .......... 16 Sector Erase Command Sequence ....... 17 Erase Suspend/Erase Resume Commands ... 17
Figure 4. Erase Operation ......18
Command Definitions .... 19
Table 5. Am29LV200B Command Definitions......... 19
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 20 DQ7: Data# Polling ........ 20
Figure 5. Data# Polling Algorithm .........20
RY/BY#: Ready/Busy# .. 21 DQ6: Toggle Bit I ........... 21 DQ2: Toggle Bit II .......... 21 Reading Toggle Bits DQ6/DQ2 .... 21 DQ5: Exceeded Timing Limits ...... 22 DQ3: Sector Erase Timer ....... 22
Figure 6. Toggle Bit Algorithm .........22 Table 6. Write Operation Status...... 23
Erase and Programming Performance . . . . . . . 39 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 39 TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 39 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 40 TS 048--48-Pin Standard TSOP ........... 40 TSR048--48-Pin Reverse TSOP .......... 41 SO 044--44-Pin Small Outline Package ........ 42 FBA048--48-Ball Fine-Pitch Ball Grid Array, 0.80 mm pitch, 6 x 8 mm package ......... 43 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 44 Revision A (January 1998) ..... 44 Revision B (July 1998) ... 44 Revision C (January 1999) ..... 44 Revision C+1 (March 27, 1999) .... 44 Revision C+2 (May 17, 1999) ....... 44 Revision C+3 (June 1, 1999) ........ 44 Revision C+4 (July 2, 1999) ......... 44 Revision C+5 (August 25, 1999) ............ 44 Revision D (November 18, 1999) .......... 44 Revision D+1 (November 13, 2000) ...... 44 Revision D+2 (April 12, 2002) ....... 44
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 24
April 12, 2002
Am29LV200B
3
PRODUCT SELECTOR GUIDE
Family Part Number Speed Options Regulated Voltage Range: VCC = 3.03.6 V Full Voltage Range: VCC = 2.73.6 V Max access time, ns (tACC ) Max CE# access time, ns (tCE) Max OE# access time, ns (tOE ) Note: See "AC Characteristics" for full specifications. 55 55 30 5 5R 70 70 70 30 90 90 90 35 120 120 120 50 Am29LV200B
BLOCK DIAGRAM
R Y /B Y # VC C VSS RESET# Erase Voltage Generator Inp u t/O utp u t Buffers Sector Switches DQ0DQ15 (A-1)
WE# BYTE#
S ta te C ontr ol Command R e g i s te r
P GM Voltage Generator Chip Enable Output Enable Logic ST B Data L a tc h
C E# O E#
ST B VC C Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A 0 A 16
4
Am29LV200B
April 12, 2002
CONNECTION DIAGRAMS
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# NC NC A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Standard TSOP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Reverse TSOP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# NC NC A7 A6 A5 A4 A3 A2 A1
April 12, 2002
Am29LV200B
5
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