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Part: AM29LV116BT-120EI
Category:
Memory
-> Flash
Description: 16 Megabit ( 2 M X 8-bit ) CMOS 3.0 Volt-only Boot Sector Flash Memory
Company: Advanced Micro Devices, Inc.
Datasheet: Download AM29LV116BT-120EI datasheet File size : 1359 kB
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Datasheet text preview:
PRELIMINARY
Am29LV116B
16 Megabit (2 M x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s Single power supply operation -- Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications -- Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors s Manufactured on 0.35 µm process technology s High performance -- Full voltage range: access times as fast as 90 ns -- Regulated voltage range: access times as fast as 80 ns s Ultra low power consumption (typical values at 5 MHz) -- 200 nA Automatic Sleep mode current -- 200 nA standby mode current -- 9 mA read current -- 15 mA program/erase current s Flexible sector architecture -- One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-one 64 Kbyte sectors -- Suppor ts full chip erase -- Sector Protection features: A hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked in-system or via programming equipment Temporar y Sector Unprotect feature allows code changes in previously locked sectors s Unlock Bypass Program Command -- Reduces overall programming time when issuing multiple program command sequences s Top or bottom boot block configurations available s Embedded Algorithms -- Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors -- Embedded Program algorithm automatically writes and verifies data at specified addresses s Minimum 1,000,000 write cycle guarantee per sector s Package option -- 40-pin TSOP s CFI (Common Flash Interface) compliant -- Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices s Compatibility with JEDEC standards -- Pinout and software compatible with singlepower supply Flash -- Superior inadvertent write protection s Data# Polling and toggle bits -- Provides a software method of detecting program or erase operation completion s Ready/Busy# pin (RY/BY#) -- Provides a hardware method of detecting program or erase cycle completion s Erase Suspend/Erase Resume -- Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation s Hardware reset pin (RESET#) -- Hardware method to reset the device to reading array data
This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Publication# 21359 Rev: C Amendment/+2 Issue Date: March 1998
PRELIMINARY
GENERAL DESCRIPTION
T h e Am29LV116B is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2,097,152 bytes. The device is offered in a 40-pin TSOP package. The byte-wide (x8) d ata appears on DQ7DQ0. All read, program, and erase operations are accomplished using only a single power supply. The device can also be programmed in standard EPROM programmers. The standard device offers access times of 80, 90, and 1 2 0 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 3.0 volt power supply for both read and write functions. Internally genera t e d and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Comm a n d s are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that co ntr ol s the erase and programming circuitry. Write cycles also internally latch addresses and data needed fo r the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program c o m m a n d sequence. This initiates the Embedded Program algorithm--an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm--an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the d a t a contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memor y. This can be achieved in-system or via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. T h e device offers two power-saving features. When addresses have been stable for a specified amount of tim e, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. A M D 's Flash technology combines years of Flash m e m o r y manufacturing experience to produce the highest levels of quality, reliability and cost effectiven e s s. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunn e l i n g . The data is programmed using hot electron inject ion.
Am29LV116B
2
PRELIMINARY
PRODUCT SELECTOR GUIDE
Family Part Number Speed Options Regulated Voltage Range: VCC =3.03.6 V Full Voltage Range: VCC = 2.73.6 V Max access time, ns (tACC) Max CE# access time, ns (tCE) Max OE# access time, ns (tOE) 80 80 30 80R 90 90 90 35 120 120 120 50 Am29LV116B
Note: See "AC Characteristics" for full specifications.
BLOCK DIAGRAM
RY/BY# VCC V SS RESET# Erase Voltage Generator Input/Output Buffers Sector Switches DQ0DQ7
WE#
State Control Command Register
PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE# OE#
STB VCC Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0A20
21359C-1
3
Am29LV116B
PRELIMINARY
CONNECTION DIAGRAMS
A16 A15 A14 A13 A12 A11 A9 A8 WE# RESET# NC RY/BY# A18 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40-Pin Standard TSOP
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
A17 VSS A20 A19 A10 DQ7 DQ6 DQ5 DQ4 VCC VCC NC DQ3 DQ2 DQ1 DQ0 OE# VSS CE# A0
A17 VSS A20 A19 A10 DQ7 DQ6 DQ5 DQ4 VCC VCC NC DQ3 DQ2 DQ1 DQ0 OE# VSS CE# A0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40-Pin Reverse TSOP
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
A16 A15 A14 A13 A12 A11 A9 A8 WE# RESET# NC RY/BY# A18 A7 A6 A5 A4 A3 A2 A1
21359C-2
Am29LV116B
4
PRELIMINARY
PIN CONFIGURATION
A0A20 = 21 addresses DQ0DQ7 = 8 data inputs/outputs C E# OE# WE# RESET# RY/BY# VCC = Chip enable = Output enable = Write enable = Hardware reset pin, active low = Ready/Busy output = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) = Device ground = Pin not connected internally
LOGIC SYMBOL
21 A0A20 DQ0DQ7 8
CE# OE# WE# RESET# RY/BY#
V SS NC
21359C-3
5
Am29LV116B
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