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Part: AM29LV040BB-70EC
Category:
Memory
-> Flash
-> 4 Mb
Description: 4 Megabit CMOS 3.0 Volt-only Uniform 32-pin Flash Memory
Company: Advanced Micro Devices, Inc.
Datasheet: Download AM29LV040BB-70EC datasheet File size : 1438 kB
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Datasheet text preview:
Am29LV040B
4 Megabit (512 K x 8-Bit) CMOS 3.0 Volt-only, Uniform Sector 32-Pin Flash Memory
DISTINCTIVE CHARACTERISTICS
s Single power supply operation -- Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications -- Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors s Manufactured on 0.32 µm process technology s High performance -- Full voltage range: access times as fast as 70 ns -- Regulated voltage range: access times as fast as 60 ns s Ultra low power consumption (typical values at 5 MHz) -- Automatic sleep mode: 1 µA -- Standby mode: 1 µA -- Read mode: 7 mA -- Program/erase mode: 15 mA s Flexible sector architecture -- Eight 64 Kbyte sectors -- Any combination of sectors can be erased; supports full chip erase -- Sector Protection features: Hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked via programming equipment s Unlock Bypass Program Command -- Reduces overall programming time when issuing multiple program command sequences s Embedded Algorithms -- Embedded Erase algorithms automatically preprogram and erase the entire chip or any combination of designated sectors -- Embedded Program algorithms automatically writes and verifies data at specified addresses s Minimum 1,000,000 write/erase cycles guaranteed s 20-year data retention at 125°C -- Reliable operation for the life of the system s Package option -- 32-pin PLCC -- 32-pin TSOP s Compatibility with JEDEC standards -- Pinout and software compatible with singlepower supply Flash -- Superior inadvertent write protection s Data# Polling and toggle bits -- Provides a software method of detecting program or erase cycle completion s Erase Suspend/Resume -- Suppor ts reading data from or programming data to a sector not being erased
This Data Sheet states AMD's current specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 21354 Rev: D Amendment/+1 Issue Date: November 13, 2000
GENERAL DESCRIPTION
The Am29LV040B is a single power supply, 4 Mbit, 3.0 Vo lt- on ly Flash memory device organized as 524,288 bytes. The data appears on DQ0-DQ7. The device is available in 32-pin PLCC and 32-pin TSOP packages. All read, erase, and program operations are accomplished using only a single power supply. The device can also be programmed in standard EPROM programmers. The device offers access times of 60, 70, 90, and 120 ns allowing high speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate control pins--chip enable (CE#), write enable (WE# ), and output enable (OE#)--to control normal read and write operations. The device requires only a single power supply (2.7 V3.6V) for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Comm a n d s are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that co ntr ol s the erase and programming circuitry. Write cycles also internally latch addresses and data needed fo r the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program c o m m a n d sequence. This initiates the Embedded Program algorithm--an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. D e v i c e erasure occurs by executing the erase c o m m a n d sequence. This initiates the Embedded Erase algorithm--an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the d a t a contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase o p e r a t i o n s in any combination of the sectors of memory. This is achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. T h e device offers two power-saving features. When addresses have been stable for a specified amount of tim e, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. A M D 's Flash technology combines years of Flash m e m o r y manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector s im ul t an e o us ly via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.
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Am29LV040B
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . 7 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 8
Table 1. Am29LV040B Device Bus Operations ........ 8
DQ5: Exceeded Timing Limits ...... 18 DQ3: Sector Erase Timer ....... 18
Table 5. Write Operation Status..... 19
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 20
Figure 5. Maximum Negative Overshoot Waveform .... 20 Figure 6. Maximum Positive Overshoot Waveform ...... 20
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 20 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ...... 22 Figure 8. Typical ICC1 vs. Frequency ............ 22
Requirements for Reading Array Data .... 8 Writing Commands/Command Sequences ...... 8 Program and Erase Operation Status ..... 9 Standby Mode ........ 9 Automatic Sleep Mode .... 9 Output Disable Mode ....... 9
Table 2. Am29LV040BT Sector Address Table ........ 9
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. Test Setup ..... 23 Table 6. Test Specifications .. 23
Key to Switching Waveforms. . . . . . . . . . . . . . . . 23
Figure 10. Input Waveforms and Measurement Levels ........ 23
Autoselect Mode ..... 9
Table 3. Am29LV040B Autoselect Codes (High Voltage Method).. 10
Sector Protection/Unprotection ..... 10 Hardware Data Protection ...... 10 Low VCC Write Inhibit ..... 10 Write Pulse "Glitch" Protection ..... 10 Logical Inhibit ........ 10 Power-Up Write Inhibit ... 10 Command Definitions . . . . . . . . . . . . . . . . . . . . . . 11 Reading Array Data ....... 11 Reset Command ............ 11 Autoselect Command Sequence ........... 11 Byte Program Command Sequence ...... 11 Unlock Bypass Command Sequence .... 12 Chip Erase Command Sequence .......... 12
Figure 1. Program Operation ..........12
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 24 Read Operations ........... 24
Figure 11. Read Operations Timings ............ 24
Erase/Program Operations ..... 25
Figure 12. Program Operation Timings ......... 26 Figure 13. Chip/Sector Erase Operation Timings .. 26 Figure 14. Data# Polling Timings (During Embedded Algorithms) . 27 Figure 15. Toggle Bit Timings (During Embedded Algorithms) ...... 27 Figure 16. DQ2 vs. DQ6 ........ 28
Alternate CE# Controlled Erase/Program Operations ... 29
Figure 17. Alternate CE# Controlled Write Operation Timings ...... 30
Sector Erase Command Sequence ....... 13 Erase Suspend/Erase Resume Commands ... 13
Figure 2. Erase Operation ......14
Command Definitions .... 15
Table 4. Am29LV040B Command Definitions......... 15
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 16 DQ7: Data# Polling ........ 16
Figure 3. Data# Polling Algorithm .........16
DQ6: Toggle Bit I ........... 17 DQ2: Toggle Bit II .......... 17 Reading Toggle Bits DQ6/DQ2 .... 17
Figure 4. Toggle Bit Algorithm .........18
Erase and Programming Performance . . . . . . . 31 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 31 TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 31 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 32 TS 032--32-Pin Standard TSOP ........... 32 TSR032--32-Pin Reverse TSOP .......... 33 PL 032--32-Pin Plastic Leaded Chip Carrier ....... 34 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 35 Revision A (January 1998) ..... 35 Revision B (April 1998) .. 35 Revision B+1 (November 1998) ............ 35 Revision C (January 1999) ..... 35 Revision C+1 (May 18, 1999) ....... 35 Revision C+2 (July 20, 1999) ....... 35 Revision D (November 11, 1999) .......... 35 Revision D+1 (November 13, 2000) ...... 35
Am29LV040B
3
PRODUCT SELECTOR GUIDE
Family Part Number Speed Options Regulated Voltage Range: VCC =3.03.6 V Full Voltage Range: VCC = 2.73.6 V Max access time, ns (tACC) Max CE# access time, ns (tCE) Max OE# access time, ns (tOE) 60 60 30 -60R -70 70 70 30 -90 90 90 30 -120 120 120 35 Am29LV040B
Note: See "AC Characteristics" for full specifications.
BLOCK DIAGRAM
DQ0DQ7 VC C V SS Erase Voltage Generator Input/Output Buffers Sector Switches
WE#
State Control Command Register
PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE# OE#
STB VCC Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0A18
4
Am29LV040B
CONNECTION DIAGRAMS
VCC A12 A15 WE# A17 A16 A18
4 3 2 1 32 31 30 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VSS DQ3 DQ1 DQ2 DQ4 DQ5 DQ6
32-Pin PLCC
29 28 27 26 25 24 23 22 21
A14 A13 A8 A9 A11 OE# A10 CE# DQ7
A11 A9 A8 A13 A14 A17 WE# VCC A18 A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32-pin Standard TSOP
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32-Pin Reverse TSOP
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A11 A9 A8 A13 A14 A17 WE# VCC A18 A16 A15 A12 A7 A6 A5 A4
Am29LV040B
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