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Part: AM29LV017B-120EC
Category:
Description: 16 Megabit CMOS 3.0 Volt-only Uniform Sector Flash Memory
Company: Advanced Micro Devices, Inc.
Datasheet: Download AM29LV017B-120EC datasheet File size : 1438 kB
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Datasheet text preview:
Am29LV017B
16 Megabit (2 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s Single power supply operation -- Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications -- Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors s Manufactured on 0.32 µm process technology s High performance -- Full voltage range: access times as fast as 80 ns -- Regulated voltage range: access times as fast as 70 ns s Ultra low power consumption (typical values at 5 MHz) -- 200 nA Automatic Sleep mode current -- 200 nA standby mode current -- 9 mA read current -- 15 mA program/erase current s Flexible sector architecture -- Thirty-two 64 Kbyte sectors -- Supports full chip erase -- Sector Protection features: A hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked in-system or via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors s Unlock Bypass Program Command -- Reduces overall programming time when issuing multiple program command sequences s Embedded Algorithms -- Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors -- Embedded Program algorithm automatically writes and verifies data at specified addresses s Minimum 1,000,000 write cycle guarantee per sector s 20-year data retention at 125°C -- Reliable operation for the life of the system s Package option -- 48-ball FBGA -- 40-pin TSOP s CFI (Common Flash Interface) compliant -- Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices s Compatibility with JEDEC standards -- Pinout and software compatible with singlepower supply Flash -- Superior inadvertent write protection s Data# Polling and toggle bits -- Provides a software method of detecting program or erase operation completion s Ready/Busy# pin (RY/BY#) -- Provides a hardware method of detecting program or erase cycle completion s Erase Suspend/Erase Resume -- Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation s Hardware reset pin (RESET#) -- Hardware method to reset the device to reading array data
This Data Sheet states AMD's current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 21415 Rev: D Amendment/+1 Issue Date: April 12, 1999
GENERAL DESCRIPTION
T h e Am29LV017B is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2,097,152 bytes. The device is offered in 48-ball FBGA and 40-pin TSOP packages. T he byte-wide (x8) data appears on DQ7DQ0. All read, program, and erase operations are accomplished using only a single power supply. The device can also be programmed in standard EPROM programmers. The standard device offers access times of 70, 80, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 3.0 volt power supply for both read and write functions. Internally genera t e d and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program c o m m a n d sequence. This initiates the Embedded Program algorithm--an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm--an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the d a t a contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. A M D 's Flash technology combines years of Flash m e m o r y manufacturing experience to produce the highest levels of quality, reliability and cost effectiven e s s . The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.
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Am29LV017B
PRODUCT SELECTOR GUIDE
Family Part Number Speed Option Regulated Voltage Range: VCC =3.03.6 V Full Voltage Range: VCC = 2.73.6 V Max access time, ns (tACC) Max CE# access time, ns (tCE) Max OE# access time, ns (tOE) Note: See "AC Characteristics" for full specifications. 70 70 30 -70R -80 80 80 30 -9 0 90 90 35 -120 120 120 50 Am29LV017B
BLOCK DIAGRAM
RY/BY# VCC V SS RESET# Erase Voltage Generator Input/Output Buffers Sector Switches DQ0 D Q 7
WE#
State Co ntro l Command Register
PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE # OE#
STB VCC Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0A20
21415D-1
Am29LV017B
3
CONNECTION DIAGRAMS
A16 A15 A14 A13 A12 A11 A9 A8 WE# RESET# NC RY/BY# A18 A7 A6 A5 A4 A3 A2 A1 A17 VSS A20 A19 A10 DQ7 DQ6 DQ5 DQ4 VCC VCC NC DQ3 DQ2 DQ1 DQ0 OE# VSS CE# A0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A17 VSS A20 A19 A10 DQ7 DQ6 DQ5 DQ4 VCC VCC NC DQ3 DQ2 DQ1 DQ0 OE# VSS CE# A0 A16 A15 A14 A13 A12 A11 A9 A8 WE# RESET# NC RY/BY# A18 A7 A6 A5 A4 A3 A2 A1
40-Pin Standard TSOP
40-Pin Reverse TSOP
48-Ball FBGA (Top View, Balls Facing Down)
A6 A14 A5 A9 A4 WE# A3 RY/BY# A2 A7 A1 A3
B6 A13 B5 A8 B4 RESET# B3 NC B2 A18 B1 A4
C6 A15 C5 A11 C4 NC C3 NC C2 A6 C1 A2
D6 A16 D5 A12 D4 NC D3 NC D2 A5 D1 A1
E6 A17 E5 A19 E4 DQ5 E3 DQ2 E2 DQ0 E1 A0
F6 NC F5 A10 F4 NC F3 DQ3 F2 NC F1 CE#
G6 A20 G5 DQ6 G4 VCC G3 VCC G2 NC G1 OE#
H6 VSS H5 DQ7 H4 DQ4 H3 NC H2 DQ1 H1 VSS
21415D-2
4
Am29LV017B
Special Handling Instructions for FBGA Packages
Special handling is required for Flash Memory products in FBGA packages.
F l a s h memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.
PIN CONFIGURATION
A0A20 = 21 addresses DQ0DQ7 = 8 data inputs/outputs C E# OE# WE# RESET# RY/BY# VCC = Chip enable = Output enable = Write enable = Hardware reset pin, active low = Ready/Busy output = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) = Device ground = Pin not connected internally
LOGIC SYMBOL
21 A0A20 DQ0DQ7 8
CE# OE# WE# RESET# RY/BY#
V SS NC
21415D-3
Am29LV017B
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