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Part: AM29LV001BT-70
Category:
Memory
-> Flash
Description:
Company: Advanced Micro Devices, Inc.
Datasheet: Download AM29LV001BT-70 datasheet File size : 1438 kB
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Datasheet text preview:
Am29LV001B
1 Megabit (128 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
Single power supply operation -- Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications -- Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors Manufactured on 0.32 µm process technology High performance -- Full voltage range: access times as fast as 55 ns -- Regulated voltage range: access times as fast as 45 ns Ultra low power consumption (typical values at 5 MHz) -- 200 nA Automatic Sleep mode current -- 200 nA standby mode current -- 7 mA read current -- 15 mA program/erase current Flexible sector architecture -- One 8 Kbyte, two 4 Kbyte, and seven 16 Kbyte -- Supports full chip erase -- Sector Protection features: Hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked in-system or via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors Unlock Bypass Mode Program Command -- Reduces overall programming time when issuing multiple program command sequences Top or bottom boot block configurations available Embedded Algorithms -- Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors -- Embedded Program algorithm automatically writes and verifies data at specified addresses Minimum 1 million erase cycle guarantee per sector 20 Year data retention at 125°C -- Reliable operation for the life of the system Package option -- 32-pin TSOP -- 32-pin PLCC Compatibility with JEDEC standards -- Pinout and software compatible with singlepower supply Flash -- Superior inadvertent write protection Data# Polling and toggle bits -- Provides a software method of detecting program or erase operation completion Erase Suspend/Erase Resume -- Supports reading data from or programming data to a sector that is not being erased Hardware reset pin (RESET#) -- Hardware method for resetting the device to reading array data
This Data Sheet states AMD's current technical specifications regarding the Products described herein. This Data Shee t may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 21557 R ev: F Am endment/ 0 Issue Date: September 26, 2002
GENERAL DESCRIPTION
T h e Am29LV001B is a 1 Mbit, 3.0 Volt-only Flash m e m o r y device organized as 131,072 bytes. The Am29LV001B has a boot sector architecture. The device is offered in 32-pin PLCC and 32-pin TSOP packages. The byte-wide (x8) data appears on DQ7-DQ0. All read, erase, and program operations are accomplished using only a single power supply. The device can also be programmed in standard EPROM programmers. The standard Am29LV001B offers access times of 45, 55, 70, and 90 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single power supply (2.7 V3.6V) for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The Am29LV001B is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine t ha t controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program c o m m a n d sequence. This initiates the Embedded Program algorithm--an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequ ence . This initiates the Embedded Erase algorithm--an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the d a t a contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. T he device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. A M D's Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.
2
Am29LV001B
September 26, 2002
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 8
Table 1. Am29LV001B Device Bus Operations ........ 8
DQ3: Sector Erase Timer ....... 20
Table 6. Write Operation Status..... 21
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 22
Figure 7. Maximum Negative Overshoot Waveform .... 22 Figure 8. Maximum Positive Overshoot Waveform ...... 22
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ...... 24 Figure 10. Typical ICC1 vs. Frequency .......... 24
Requirements for Reading Array Data .... 8 Writing Commands/Command Sequences ...... 8 Program and Erase Operation Status ..... 9 Standby Mode ........ 9 Automatic Sleep Mode .... 9 RESET#: Hardware Reset Pin ....... 9 Output Disable Mode ....... 9
Table 2. Am29LV001B Top Boot Sector Architecture ........... 10 Table 3. Am29LV001B Bottom Boot Sector Architecture....... 10
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 11. Test Setup ............ 25 Table 7. Test Specifications .. 25
Key to Switching Waveforms. . . . . . . . . . . . . . . . 25
Figure 12. Input Waveforms and Measurement Levels ........ 25
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26 Read Operations ........... 26
Figure 13. Read Operations Timings ............ 26
Autoselect Mode ............ 11
Table 4. Am29LV001B Autoselect Codes...... 11
Hardware Reset (RESET#) .... 27
Figure 14. RESET# Timings .......... 27
Sector Protection/Unprotection ..... 11 Temporary Sector Unprotect ........ 11
Figure 1. In-System Sector Protect/Unprotect Algorithms ......12 Figure 2. Temporary Sector Unprotect Operation ...13
Erase/Program Operations ..... 28
Figure 15. Program Operation Timings ......... 29 Figure 16. Chip/Sector Erase Operation Timings .. 30 Figure 17. Data# Polling Timings (During Embedded Algorithms) . 31 Figure 18. Toggle Bit Timings (During Embedded Algorithms) ...... 31 Figure 19. DQ2 vs. DQ6 ........ 32
Hardware Data Protection ...... 13 Low VCC Write Inhibit ..... 13 Write Pulse "Glitch" Protection ..... 13 Logical Inhibit ........ 13 Power-Up Write Inhibit ... 13 Command Definitions . . . . . . . . . . . . . . . . . . . . . 13 Reading Array Data ....... 13 Reset Command ............ 13 Autoselect Command Sequence ........... 14 Byte Program Command Sequence ...... 14 Unlock Bypass Command Sequence .... 14
Figure 3. Program Operation ..........15
Temporary Sector Unprotect ........ 32
Figure 20. Temporary Sector Unprotect Timing Diagram ..... 32 Figure 21. In-System Sector Protect/Unprotect Timing Diagram ... 33
Alternate CE# Controlled Erase/Program Operations ... 34
Figure 22. Alternate CE# Controlled Write Operation Timings ...... 35
Chip Erase Command Sequence .......... 15 Sector Erase Command Sequence ....... 15 Erase Suspend/Erase Resume Commands ... 16
Figure 4. Erase Operation ......16
Command Definitions .... 17
Table 5. Am29LV001B Command Definitions ........ 17
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 18 DQ7: Data# Polling ........ 18
Figure 5. Data# Polling Algorithm .........18
DQ6: Toggle Bit I ........... 19 DQ2: Toggle Bit II .......... 19 Reading Toggle Bits DQ6/DQ2 .... 19
Figure 6. Toggle Bit Algorithm .........20
DQ5: Exceeded Timing Limits ...... 20
Erase and Programming Performance . . . . . . . . 35 Latchup Characteristics . . . . . . . . . . . . . . . . . . . 36 TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 36 PLCC Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 36 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 37 PL 032--32-Pin Plastic Leaded Chip Carrier ....... 37 TS 032--32-Pin Standard Thin Small Outline Package ......... 38 TSR032--32-Pin Reverse Thin Small Outline Package ......... 39 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 40 Revision A (January 1998) ..... 40 Revision A+1 (February 1998) ...... 40 Revision B (April 1998) .. 40 Revision C (April 1998) .. 40 Revision D (January 1999) ..... 40 Revision E (November 17, 1999) ........... 40 Revision E+1 (November 13, 2000) ...... 40 Revision F (September 26, 2002) .......... 40
September 26, 2002
Am29LV001B
3
PRODUCT SELECTOR GUIDE
Family Part Number Speed Options Regulated Voltage Range: VCC =3.03.6 V Full Voltage Range: VCC = 2.73.6 V Max access time, ns (tACC ) Max CE# access time, ns (tCE) Max OE# access time, ns (tOE ) 45 45 25 -45R - 55 55 55 30 - 70 70 70 30 - 90 90 90 35 Am29LV001B
Note:See "AC Characteristics" for full specifications.
BLOCK DIAGRAM
DQ0DQ7 VC C VSS RES ET# Erase Voltage Generator In put/O utp u t Buffers Sector Switches
WE#
S ta te C ontr ol Command R e g i s te r
P GM Voltage Generator Chip Enable Output Enable Logic ST B Data L a tc h
C E# O E#
S TB VC C Detector T i m er Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A 0A 16
4
Am29LV001B
September 26, 2002
CONNECTION DIAGRAMS
A11 A9 A8 A13 A14 NC WE# VCC RESET# A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32-Pin Standard TSOP
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32-Pin Reverse TSOP
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A11 A9 A8 A13 A14 NC WE# VCC RESET# A16 A15 A12 A7 A6 A5 A4
RESET#
4 3 2 1 32 31 30 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 V SS DQ3 DQ4 DQ5 DQ1 DQ2 DQ6 AmPLLV001 29CC 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE# A10 CE# DQ7
September 26, 2002
Am29LV001B
VCC
A12 A15
WE# NC
A16
5
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