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Part: AM29F200AT-70FEB
Category:
Memory
-> Flash
Description: 2 Megabit ( 256 K X 8-bit/128 K X 16-bit ) CMOS 5.0 Volt-only, Sectored Flash Memory-die Revision 1
Company: Advanced Micro Devices, Inc.
Datasheet: Download AM29F200AT-70FEB datasheet File size : 1438 kB
Request For quote: Find where to buy AM29F200AT-70FEB
Datasheet text preview:
SUPPLEMENT
Am29F200A Known Good Die
2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 5.0 Volt-only, Sectored Flash Memory--Die Revision 1
DISTINCTIVE CHARACTERISTICS
s 5.0 V ± 10% for read and write operations -- Minimizes system level power requirements s High performance -- 90 or 120 ns access time s Low power consumption -- 20 mA typical active read current (byte mode) -- 28 mA typical active read current for (word mode) -- 30 mA typical program/erase current -- 1 µA typical standby current s Sector erase architecture -- One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and three 64 Kbyte sectors (byte mode) -- One 8 Kword, two 4 Kword, one 16 Kword, and three 32 Kword sectors (word mode) -- Supports full chip erase -- Sector Protection features: A hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors s Top or bottom boot block configurations available s Embedded Algorithms -- Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors -- Embedded Program algorithm automatically writes and verifies data at specified addresses s Minimum 100,000 write/erase cycles guaranteed s Compatible with JEDEC standards -- Pinout and software compatible with single-power-supply flash -- Superior inadvertent write protection s Data# Polling and Toggle Bit -- Detects program or erase cycle completion s Ready/Busy# output (RY/BY#) -- Hardware method for detection of program or erase cycle completion s Erase Suspend/Resume -- Supports reading data from a sector not being erased s Hardware RESET# pin -- Resets internal state machine to the reading array data s Tested to datasheet specifications at temperature s Qu ality and reliability levels equivalent to standard packaged components
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P ubl ication # 21257 Rev: B Amendment/0 Issue Date: December 1997
SUPPLEMENT
GENERAL DESCRIPTION
The Am29F200A in Known Good Die (KGD) form is a 2 Mbit, 5.0 Volt-only Flash memory. AMD defines KGD as standard product in die form, tested for functionality an d speed. AMD KGD products have the same reliability and quality as AMD products in packaged form. Am29F200A Features The Am29F200A is organized as 262,144 bytes of 8 bits each or 131,072 words of 16 bits each. The 8-bit data appears on DQ0-DQ7; the 16-bit data appears on DQ0-DQ15. This device is designed to be programmed in-system with the standard system 5.0 Volt V CC supply. A 12.0 volt VPP is not required for program or erase operations. The standard Am29F200A in KGD form offers an access time of 90 or 120 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bu s contention the device has separate chip enable (CE# ), write enable (WE#), and output enable (OE#) controls. The device requires only a single 5.0 volt power supply for both read and write functions. Internally genera t e d and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serv e as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program c o m m a n d sequence. This initiates the Embedded Pro g ra m algorithm--an internal algorithm that automatica lly times the program pulse widths and verifies proper cell margin. Dev ice erasure occurs by executing the erase comman d sequence. This initiates the Embedded Erase a l g o ri t h m -- a n internal algorithm that automatically p r e p r o g r a m s the array ( i f it is not already pro-
gramm ed) before executing the erase operation. Durin g erase, the device automatically times the erase pul se widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6/ DQ2 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the d a t a contents of other sectors. The device is fully erased when shipped from the factory. Har dw a re data protection measures include a low V CC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The system can place the device into the standby mode. Power consumption is greatly reduced in this mode. AMD's Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultan e o u s l y via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.
ELECTRICAL SPECIFICATIONS
R e f e r to the Am29F200A data sheet, publication number 20380, for full electrical specifications on the Am 2 9 F 2 0 0 A.
PRODUCT SELECTOR GUIDE
Family Part Number Speed Option (VCC = 5.0 V ± 10%) Max access time, ns (tACC) Max CE# access time, ns (tCE) Max OE# access time, ns (tO E) -90 90 90 35 Am29F200A KGD -120 120 120 50
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SUPPLEMENT
DIE PHOTOGRAPH
Orientation relative to top left corner of Gel-Pak
Orientation relative to leading edge of tape and reel
DIE PAD LOCATIONS
9 10 11 12 8 7 6 5 4 3 2 1 42 41 40 39 38 37 36 35 34 33 32 31
AMD logo location
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 30 29 28
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SUPPLEMENT
PAD DESCRIPTION
Pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Signal VCC DQ4 DQ12 DQ5 DQ13 DQ6 DQ14 DQ7 DQ15/A-1 V SS BYTE# A16 A15 A14 A13 A12 A11 A10 A9 A8 W E# RESET# RY/BY# A7 A6 A5 A4 A3 A2 A1 A0 CE# V SS OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 Pad Center (mils) X Y 0 .0 0 .0 8 .5 1 .2 1 7 .3 1 .2 2 6 .1 1 .2 3 4 .9 1 .2 4 3 .6 1 .2 5 2 .4 1 .2 6 1 .2 1 .2 6 9 .9 1 .2 8 0 .2 2 .7 8 2 .3 1 3 .5 8 2 .3 2 4 .1 8 2 .3 128.4 8 2 .3 138.7 8 2 .3 150.0 6 8 .2 150.0 5 7 .9 150.0 4 7 .6 150.0 3 6 .7 150.0 2 6 .4 150.0 1 6 .1 150.0 5 .2 150.0 2 6 .1 150.0 5 0 .2 150.0 6 0 .5 150.0 7 0 .8 150.0 8 1 .1 150.0 9 1 .4 150.0 9 1 .5 138.7 9 1 .5 128.4 9 1 .5 2 4 .1 9 1 .5 1 3 .6 9 1 .1 1 .8 7 9 .8 0 .7 7 0 .0 1 .2 6 1 .3 1 .2 5 2 .5 1 .2 4 3 .7 1 .2 3 4 .9 1 .2 2 6 .2 1 .2 1 7 .4 1 .2 8 .6 1 .2 Pad Center (millimeters) X Y 0.0000 0.0000 0.2159 0.0305 0.4394 0.0305 0.6629 0.0305 0.8865 0.0305 1.1074 0.0305 1.3310 0.0305 1.5545 0.0305 1.7755 0.0305 2.0371 0.0686 2.0904 0.3429 2.0904 0.6121 2.0904 3.2614 2.0904 3.5230 2.0904 3.8100 1.7323 3.8100 1.4707 3.8100 1.2090 3.8100 0.9322 3.8100 0.6706 3.8100 0.4089 3.8100 0.1321 3.8100 0.6629 3.8100 1.2751 3.8100 1.5367 3.8100 1.7983 3.8100 2.0599 3.8100 2.3216 3.8100 2.3241 3.5230 2.3241 3.2614 2.3241 0.6121 2.3241 0.3454 2.3139 0.0457 2.0269 0.0178 1.7780 0.0305 1.5570 0.0305 1.3335 0.0305 1.1100 0.0305 0.8865 0.0305 0.6655 0.0305 0.4420 0.0305 0.2184 0.0305
Note: The coordinates above are relative to the center of pad 1 and can be used to operate wire bonding equipment.
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SUPPLEMENT
ORDERING INFORMATION Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Am29F200A T -90 DP C 1 DIE REVISION This number refers to the specific AMD manufacturing process and product technology reflected in this document. It is entered in the revision field of AMD standard product nomenclature. TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (40°C to +85°C) E = Extended (55°C to +125°C) PACKAGE TYPE AND MINIMUM ORDER QUANTITY DP = Waffle Pack 245 die per 5 tray stack DG = DT = DW = Gel-Pak® Die Tray 486 die per 6 tray stack SurftapeTM (Tape and Reel) 2500 per 7-inch reel Gel-Pak® Wafer Tray (sawn wafer on frame) Call AMD sales office for minimum order quantity
SPEED OPTION See Valid Combinations
BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector
DEVICE NUMBER/DESCRIPTION Am29F200A Known Good Die 2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS Flash Memory--Die Revision 1 5.0 Volt-only Read, Program, and Erase
Valid Combinations Am29F200AT-90, Am29F200AB-90 Am29F200AT-120, Am29F200AB-120 DPC 1, DPI 1, DPE 1, DGC 1, DGI 1, DGE 1, DTC 1, DTI 1, DTE 1, DWC 1, DWI 1, DWE 1
Valid Combinations Va li d Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
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