|
|
Part: AM29F040B-70FI
Category:
Memory
-> Flash
Description: 4 Megabit ( 512 K X 8-bit ) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
Company: Advanced Micro Devices, Inc.
Datasheet: Download AM29F040B-70FI datasheet File size : 1143 kB
Request For quote: Find where to buy AM29F040B-70FI
Datasheet text preview:
Am29F040B
4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s 5.0 V ± 10% for read and write operations -- Minimizes system level power requirements s Manufactured on 0.32 µm process technology -- Compatible with 0.5 µm Am29F040 device s High performance -- Access times as fast as 55 ns s Low power consumption -- 20 mA typical active read current -- 30 mA typical program/erase current -- 1 µA typical standby current (standard access time to active mode) s Flexible sector architecture -- 8 uniform sectors of 64 Kbytes each -- Any combination of sectors can be erased -- Suppor ts full chip erase -- Sector protection: A hardware method of locking sectors to prevent any program or erase operations within that sector s Embedded Algorithms -- Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors -- Embedded Program algorithm automatically writes and verifies bytes at specified addresses s Minimum 1,000,000 program/erase cycles per sector guaranteed s 20-year data retention at 125°C -- Reliable operation for the life of the system s Package options -- 32-pin PLCC, TSOP, or PDIP s Compatible with JEDEC standards -- Pinout and software compatible with single-power-supply Flash standard -- Superior inadvertent write protection s Data# Polling and toggle bits -- Provides a software method of detecting program or erase cycle completion s Erase Suspend/Erase Resume -- Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation
This Data Sheet states AMD's current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 21445 Rev: E Amendment/0 Issue Date: November 29, 2000
GENERAL DESCRIPTION
The Am29F040B is a 4 Mbit, 5.0 volt-only Flash memory organized as 524,288 Kbytes of 8 bits each. The 512 Kbytes of data are divided into eight sectors of 64 Kbytes each for flexible erase capability. The 8 bits of data appear on DQ0DQ7. The Am29F040B is offered in 32-pin PLCC, TSOP, and PDIP packages. This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply. A 12.0 volt VPP is not required for write or erase operations. The device can also be programmed in standard EPROM programmers. This device is manufactured using AMD's 0.32 µm proc e s s technology, and offers all the features and benefits of the Am29F040, which was manufactured u s i n g 0.5 µm process technology. In addtion, the Am29F040B has a second toggle bit, DQ2, and also offers the ability to program in the Erase Suspend mode. The standard Am29F040B offers access times of 55, 70, 90, 120, and 150 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 5.0 volt power supp l y for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Comm a n d s are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed fo r the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program c o m m a n d sequence. This initiates the Embedded Program algorithm--an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase a lg o r i t h m -- a n internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the d a t a contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memor y. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The system can place the device into the standby mode. Power consumption is greatly reduced in this mode. A M D 's Flash technology combines years of Flash m e m o r y manufacturing experience to produce the highest levels of quality, reliability and cost effectiven e ss. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.
2
Am 2 9 F 0 4 0 B
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . Device Bus Operations . . . . . . . . . . . . . . . . . . . . . Requirements for Reading Array Data .... Writing Commands/Command Sequences ...... Program and Erase Operation Status ..... Standby Mode ........ Output Disable Mode....... 4 4 5 6 6 7 8 8 8 8 8 9 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 19
Figure 5. Maximum Negative Overshoot Waveform ............ 19 Figure 6. Maximum Positive Overshoot Waveform ..... 19
Table 1. Am29F040B Device Bus Operations ..8
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 19 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 20 TTL/NMOS Compatible .......... 20 CMOS Compatible......... 20 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7. Test Setup............ 21 Table 6. Test Specifications .. 21
Key to Switching Waveforms. . . . . . . . . . . . . . . . 21 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 22 Read Only Operations ... 22
Figure 8. Read Operation Timings ...... 22
Table 2. Sector Addresses Table ......9
Autoselect Mode............ 10
Table 3. Am29F040B Autoselect Codes (High Voltage Method) .....10
Erase and Program Operations .... 23
Figure 9. Program Operation Timings.......... Figure 10. Chip/Sector Erase Operation Timings ....... Figure 11. Data# Polling Timings (During Embedded Algorithms) Figure 12. Toggle Bit Timings (During Embedded Algorithms)..... Figure 13. DQ2 vs. DQ6....... 24 24 25 25 26
Sector Protection/Unprotection..... 10 Hardware Data Protection ...... 10
Low VCC Write Inhibit .... 10 Write Pulse "Glitch" Protection ........ 10 Logical Inhibit .......... 10 Power-Up Write Inhibit ........... 10
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 27 Erase and Program Operations .... 27
Alternate CE# Controlled Writes .... 27 Figure 14. Alternate CE# Controlled Write Operation Timings ..... 28
Command Definitions . . . . . . . . . . . . . . . . . . . . . 11 Reading Array Data ....... 11 Reset Command............ 11 Autoselect Command Sequence ........... 11 Byte Program Command Sequence...... 11
Figure 1. Program Operation ......... 12
Chip Erase Command Sequence .......... 12 Sector Erase Command Sequence ....... 12 Erase Suspend/Erase Resume Commands... 13
Figure 2. Erase Operation..... 13
Command Definitions .... 14
Table 4. Am29F040B Command Definitions...14
Write Operation Status . . . . . . . . . . . . . . . . . . . . 15 DQ7: Data# Polling........ 15
Figure 3. Data# Polling Algorithm ........ 15
DQ6: Toggle Bit I ........... DQ2: Toggle Bit II .......... Reading Toggle Bits DQ6/DQ2 .... DQ5: Exceeded Timing Limits ...... DQ3: Sector Erase Timer .......
16 16 16 16 17
Figure 4. Toggle Bit Algorithm........ 17 Table 5. Write Operation Status.......18
Erase and Programming Performance . . . . . . . . 29 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 29 TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . 29 PLCC and PDIP Pin Capacitance. . . . . . . . . . . . . 30 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 31 PD 032--32-Pin Plastic DIP ......... 31 PL 032--32-Pin Plastic Leaded Chip Carrier ....... 32 TS 032--32-Pin Standard Thin Small Package.... 33 TSR032--32-Pin Reversed Thin Small Outline Package....... 34 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 35 Revision A (May 1997) .. 35 Revision B (January 1998) ..... 35 Revision B+1 (January 1998) ....... 35 Revision B+2 (April 1998)....... 35 Revision C (January 1999) ..... 35 Revision C+1 (February 1999) ..... 35 Revision C+2 (May 17, 1999) ....... 35 Revision D (November 15, 1999) .......... 35 Revision E (November 29, 2000)........... 35
Am29F040B
3
PRODUCT SELECTOR GUIDE
Family Part Number Speed Option VCC = 5.0 V ± 5% VCC = 5.0 V ± 10% 55 55 25 -55 -70 70 70 30 -90 90 90 35 -120 120 120 50 -150 150 150 55 Am29F040B
Max access time, ns (tACC) Max CE# access time, ns (tCE) Max OE# access time, ns (tOE)
Note: See the "AC Characteristics" section for more information.
BLOCK DIAGRAM
DQ0DQ7 VCC VSS Erase Voltage Generator Input/Output Buffers
WE#
State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE# OE#
STB VCC Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0A18
4
Am 2 9 F 0 4 0 B
CONNECTION DIAGRAMS
A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VS S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PDIP 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC
WE#
VCC
A12
A15
A16
A18
A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3
4 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13
3
2
1 32 31 30 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE# A10 CE# DQ7
PLCC
14 15 16 17 18 19 20 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 A11 A9 A8 A13 A14 A17 WE# VCC A18 A16 A15 A12 A7 A6 A5 A4 VSS
A11 A9 A8 A13 A14 A17 WE# VCC A18 A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32-Pin Standard TSOP
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32-Pin Reverse TSOP
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
Am29F040B
A17
WE#
5
Others parts begin by am
AM-1 AM-2 AM-3 AM-4 AM-5 AM-6 AM-7 AM-8 AM-9 AM-10 AM-11 AM-12 AM-13 AM-14 AM-15 AM-16 AM-17 AM-18 AM-19 AM-20 AM-21 AM-22 AM-23 AM-24 AM-25 AM-26 AM-27 AM-28 AM-29 AM-30 AM-31 AM-32 AM-33 AM-34 AM-35 AM-36 AM-37 AM-38 AM-39 AM-40 AM-41 AM-42 AM-43 AM-44 AM-45 AM-46 AM-47 AM-48 AM-49 AM-50 AM-51 AM-52 AM-53 AM-54 AM-55 AM-56 AM-57 AM-58 AM-59 AM-60 AM-61 AM-62 AM-63 AM-64 AM-65 AM-66 AM-67 AM-68 AM-69 AM-70 AM-71 AM-72 AM-73 AM-74 AM-75 AM-76 AM-77 AM-78 AM-79 AM-80 AM-81 AM-82 AM-83 AM-84 AM-85 AM-86 AM-87 AM-88 AM-89 AM-90 AM-91 AM-92 AM-93 AM-94 AM-95 AM-96 AM-97 AM-98 AM-99 AM-100 AM-101 AM-102 AM-103 AM-104 AM-105
|
|
|
