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Part: AM29F017B-120FC
Category:
Memory
-> Flash
Description: 16 Megabit ( 2 M X 8-bit ) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
Company: Advanced Micro Devices, Inc.
Datasheet: Download AM29F017B-120FC datasheet File size : 1483 kB
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Datasheet text preview:
PRELIMINARY
Am29F017B
16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s Optimized for memory card applications -- Backwards-compatible with the Am29F016C s 5.0 V ± 10%, single power supply operation -- Minimizes system level power requirements s Manufactured on 0.35 µm process technology s High performance -- Access times as fast as 70 ns s Low power consumption -- 25 mA typical active read current -- 30 mA typical program/erase current -- 1 µA typical standby current (standard access time to active mode) s Flexible sector architecture -- 32 uniform sectors of 64 Kbytes each -- Any combination of sectors can be erased. -- Suppor ts full chip erase -- Group sector protection: A hardware method of locking sector groups to prevent any program or erase operations within that sector group Temporar y Sector Group Unprotect allows code changes in previously locked sectors s Embedded Algorithms -- Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors -- Embedded Program algorithm automatically writes and verifies bytes at specified addresses s Minimum 1,000,000 program/erase cycles per sector guaranteed s Package options -- 48-pin TSOP s Compatible with JEDEC standards -- Pinout and software compatible with single-power-supply Flash standard -- Superior inadvertent write protection s Data# Polling and toggle bits -- Provides a software method of detecting program or erase cycle completion s Ready/Busy# output (RY/BY#) -- Provides a hardware method for detecting program or erase cycle completion s Erase Suspend/Erase Resume -- Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation s Hardware reset pin (RESET#) -- Resets internal state machine to the read mode
Publication# 21195 Rev: B Amendment/+2 Issue Date: April 1998
PRELIMINARY
GENERAL DESCRIPTION
The Am29F017B is a 16 Mbit, 5.0 volt-only Flash memor y organized as 2,097,152 bytes. The 8 bits of data appear on DQ0DQ7. The Am29F017B is offered in a 48-pin TSOP package. This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply. A 12.0 volt VPP is not required for program or erase operations. The device can also be programmed in standard EPROM programmers. T h i s device is manufactured using AMD's 0.35 µm process technology, and offers all the features and bene f i t s of the Am29F016C, which was manufactured using 0.5 µm process technology. The standard device offers access times of 70, 90, 120, and 150 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE#), write enable (WE#), and output enable (OE#) controls. The device requires only a single 5.0 volt power supply for both read and write functions. Internally genera t e d and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents ser ve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program c o m m a n d sequence. This initiates the Embedded Program algorithm--an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase a l g o r i t h m -- a n internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the d a t a contents of other sectors. The device is fully erased when shipped from the factory. Hardw are data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. T h e system can place the device into the standby m o d e . Power consumption is greatly reduced in t h i s mode. A M D 's Flash technology combines years of Flash m e m o r y manufacturing experience to produce the h i g h e s t l e v e l s o f q u a l i t y, r e l i a b i l i t y a n d c o s t e f f e c t i v e n e s s . The device electrically erases all bits within a sector simultaneously via F o w l e r -N o r d h e i m t u n n e l i n g . T h e d a t a i s p r o g ra m m e d using hot electron injection.
2
Am 2 9 F 0 1 7 B
PRELIMINARY
PRODUCT SELECTOR GUIDE
Family Part Number Speed Options (VCC = 5.0 V ± 10% Max Access Time (ns) CE# Access (ns) OE# Access (ns) -70 70 70 40 -90 90 90 40 Am29F017B -120 120 120 50 -150 150 150 75
Note: See the AC Characteristics section for more information.
BLOCK DIAGRAM
DQ0DQ7 VCC V SS RY/BY# RESET# State Control Command Register Sector Switches Erase Voltage Generator Input/Output Buffers
WE#
PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE# OE#
STB VCC Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0A20
21195B-1
Am29F017B
3
PRELIMINARY
CONNECTION DIAGRAMS
NC NC A19 A18 A17 A16 A15 A14 A13 A12 CE# VCC NC RESET# A11 A10 A9 A8 A7 A6 A5 A4 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 NC 47 NC 46 A20 45 NC 44 WE# 43 OE# 42 RY/BY# 41 DQ7 40 DQ6 39 DQ5 38 DQ4 37 VCC 36 VSS 35 VSS 34 DQ3 33 DQ2 32 DQ1 31 DQ0 30 A0 29 A1 28 A2 27 A3 26 NC 25 NC
48-Pin Standard TSOP
21195B-2
NC NC A20 NC WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ4 VCC VSS VSS DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC A19 A18 A17 A16 A15 A14 A13 A12 CE# VCC NC RESET# A11 A10 A9 A8 A7 A6 A5 A4 NC NC
48-Pin Reverse TSOP
21195B-3
4
Am 2 9 F 0 1 7 B
PRELIMINARY
PIN CONFIGURATION
A0A20 C E# WE# OE# RESET# RY/BY# VCC = = = = = = 21 Addresses 8 Data Inputs/Outputs Chip Enable Write Enable Output Enable Hardware Reset Pin, Active Low Ready/Busy Output DQ0DQ7 =
LOGIC SYMBOL
21 A0A20 DQ0DQ7 8
CE# OE# WE# RESET# RY/BY#
= +5.0 V single power supply (see Product Selector Guide for device speed ratings and voltage supply tolerances) = = Device Ground Pin Not Connected Internally
V SS NC
21195B-4
Am29F017B
5
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