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Part: AM29F002B-120JI
Category:
Memory
Description: 2 Megabit ( 256 K X 8-bit ) CMOS 5.0 Volt-only Boot Sector Flash Memory
Company: Advanced Micro Devices, Inc.
Datasheet: Download AM29F002B-120JI datasheet File size : 1483 kB
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PRELIMINARY
Am29F002/Am29F002N
2 Megabit (256 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s Single power supply operation -- 5.0 Volt-only operation for read, erase, and program operations -- Minimizes system level requirements s High performance -- Access times as fast as 55 ns s Low power consumption (typical values at 5 MHz) -- 1 µA standby mode current -- 20 mA read current -- 30 mA program/erase current s Flexible sector architecture -- One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and three 64 Kbyte sectors -- Suppor ts full chip erase -- Sector Protection features: A hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked via programming equipment Temporar y Sector Unprotect feature allows code changes in previously locked sectors s Top or bottom boot block configurations available s Embedded Algorithms -- Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors -- Embedded Program algorithm automatically writes and verifies data at specified addresses s Minimum 100,000 write cycle guarantee per sector s Package option -- 32-pin PDIP -- 32-pin TSOP -- 32-pin PLCC s Compatibility with JEDEC standards -- Pinout and software compatible with singlepower supply Flash -- Superior inadvertent write protection s Data# Polling and toggle bits -- Provides a software method of detecting program or erase operation completion s Erase Suspend/Erase Resume -- Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation s Hardware reset pin (RESET#) -- Hardware method to reset the device to reading array data (not available on Am29F002N)
Publication# 20818 Rev: C Amendment/+2 Issue Date: March 1998
PRELIMINARY
GENERAL DESCRIPTION
The Am29F002 Family consists of 2 Mbit, 5.0 volt-only Flash memory devices organized as 262,144 bytes. T h e Am29F002 offers the RESET# function, the A m 2 9 F 0 0 2 N does not. The data appears on DQ7 D Q0 . The device is offered in 32-pin PLCC, 32-pin T S O P , and 32-pin PDIP packages. This device is d e s i g n e d to be programmed in-system with the s t a n d a r d system 5.0 volt V C C supply. No V P P is required for write or erase operations. The device can a l so be programmed in standard EPROM programmers. The standard device offers access times of 55, 70, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention t h e device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 5.0 volt power supply for both read and write functions. Internally genera t e d and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Comm a n d s are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that co ntr ol s the erase and programming circuitry. Write cycles also internally latch addresses and data needed fo r the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program c o m m a n d sequence. This initiates the Embedded Program algorithm--an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase a lg o r i t h m -- a n internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the d a t a contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memor y. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. (This feature is not available on the Am29F002N.) T h e system can place the device into the standby mode. Power consumption is greatly reduced in this mode. A M D 's Flash technology combines years of Flash m e m o r y manufacturing experience to produce the highest levels of quality, reliability and cost effectiven e s s. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunn e l i n g . The data is programmed using hot electron inject ion.
2
Am29F002/Am29F002N
PRELIMINARY
PRODUCT SELECTOR GUIDE
Family Part Number Speed Option VCC = 5.0 V ± 5% VCC = 5.0 V ± 10% Max access time, ns (tACC) Max CE# access time, ns (tCE) Max OE# access time, ns (tOE) 55 55 30 -55 -70 70 70 30 -90 90 90 35 -120 120 120 50 Am29F002/Am29F002N
Note: See "AC Characteristics" for full specifications.
BLOCK DIAGRAM
DQ0DQ7 VCC V SS RESET#
n/a Am29F00N
Sector Switches Erase Voltage Generator Input/Output Buffers
WE#
State Control Command Register
PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE# OE#
STB VCC Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0A17
20818C-1
Am29F002/Am29F002N
3
PRELIMINARY
CONNECTION DIAGRAMS
NC on Am29F00N NC on Am29F00N
RESET# NC
1 2 3 4 5 6 7 8 PDIP 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC A16 A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 A12 A15 WE#
RESET#
A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
432
1 32 31 30 29 28 27 26 A14 A13 A8 A9 A11 OE# A10 CE# DQ7
PLCC
VCC
A16
WE# A17 25 24 23 22 21 DQ5 DQ6
14 15 16 17 18 19 20 DQ1 DQ2 DQ3 VSS DQ4
NC on Am29F00N
A11 A9 A8 A13 A14 A17 WE# VCC RESET# A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Standard TSOP
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
20818C-2
4
Am29F002/Am29F002N
PRELIMINARY
PIN CONFIGURATION
A0A17 = 18 addresses DQ0DQ7 = 8 data inputs/outputs C E# OE# WE# RESET# VCC = Chip enable = Output enable = Write enable = Hardware reset pin, active low (not available on Am29F002N) = +5.0 V single power supply (see Product Selector Guide for device speed ratings and voltage supply tolerances) = Device ground = Pin not connected internally
LOGIC SYMBOL
18 A0A17 DQ0DQ7 8
CE# OE# WE# RESET#
N/C on Am29F002N
V SS NC
20818C-3
Am29F002/Am29F002N
5
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