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Part: Am29DS323DT110
Category:
Memory
-> Flash
-> 32 Mb
Description:
Company: Advanced Micro Devices, Inc.
Datasheet: Download Am29DS323DT110 datasheet File size : 1483 kB
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Datasheet text preview:
PRELIMINARY
Am29DS323D
32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES s Simultaneous Read/Write operations -- Data can be continuously read from one bank while executing erase/program functions in other bank -- Zero latency between read and write operations s Multiple bank architectures -- Two devices available with different bank sizes (refer to Table 3) s Secured Silicon (SecSiTM) Sector -- Factor y locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data -- Customer lockable: Can be read, programmed, or erased just like other sectors. Once locked, data cannot be changed -- 64 Kbyte sector size s Zero Power Operation -- Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero s Package options -- 48-ball FBGA -- 48-pin TSOP s Top or bottom boot block s Manufactured on 0.23 µm process technology s Compatible with JEDEC standards -- Pinout and software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS s High performance -- Access time as fast 110 ns -- Program time: 13 µs/word typical; with Accelerate function, 7 µs/word typical s Ultra low power consumption (typical values) -- 1 mA active read current at 1 MHz -- 5 mA active read current at 5 MHz -- 200 nA in standby or automatic sleep mode s Minimum 1 million write cycles guaranteed per sector s 20 Year data retention at 125°C -- Reliable operation for the life of the system SOFTWARE FEATURES s Data Management Software (DMS) -- AMD-supplied software manages data programming and erasing, enabling EEPROM emulation -- Eases sector erase limitations s Supports Common Flash Memory Interface (CFI) s Erase Suspend/Erase Resume -- Suspends erase operations to allow programming in same bank s Data# Polling and Toggle Bits -- Provides a software method of detecting the status of program or erase cycles s Unlock Bypass Program command -- Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES s Any combination of sectors can be erased s Ready/Busy# output (RY/BY#) -- Hardware method for detecting program or erase cycle completion s Hardware reset pin (RESET#) -- Hardware method of resetting the internal state machine to reading array data s WP#/ACC input pin -- Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status -- Acceleration (ACC) function provides accelerated program times s Sector protection -- Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector -- Temporar y Sector Unprotect allows changing data in protected sectors in-system
This Data Sheet states AMD's current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 23480 Rev: A Amendment/+3 Issue Date: November 22, 2000
Refer to AMD's Website (www.amd.com) for the latest information.
PRELIMINARY
GENERAL DESCRIPTION
The Am29DS323D family consists of 32 megabit, 1.8 v o l t - o n l y flas h mem o r y devices, o r g a n i z e d a s 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. Word mode data appears on DQ0DQ15; byte mode data appears on DQ0DQ7. The device is designed to be programmed in-system with the standard 1.8 volt VCC supply, and can also be programmed in standard EPROM programmers. The device is available with an access time of 110 and 1 2 0 ns. The devices are offered in an 48-ball FBGA p ackag e. Standard control pins--chip enable (CE#), write enable (WE#), and output enable (OE#)--control nor mal read and write operations, and avoid bus contention issues. The device requires only a single 1.8 volt power supp l y for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, a s opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs t o state which piece of data is to be updated, and where the updated data is located in the system. This i s a n a d va n t a g e c o m p a r e d t o s y s te m s w h e r e user-wr itten software must keep track of the old data l o cation , status, logical to physical translation of the d a ta onto the Flash memory device (or memory device s), and more. Using DMS, user-written software does not need to interface with the Flash memory directly. Instead, the user's software accesses the Flash memor y by calling one of only six functions. AMD prov i d e s this software to simplify system design and software integration efforts. The device offers complete compatibility with the J E D E C single-power-supply Flash command set s t a n d a rd . Commands are written to the command register using standard microprocessor write timings. R e a d i n g data out of the device is similar to reading from other Flash or EPROM devices. T h e host system can detect whether a program or erase operation is complete by using the device stat u s bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. H a rdw a re data protection measures include a low V C C detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memo r y. T h i s c a n b e a c h i e v e d i n - s y s t e m o r v i a programming equipment. T h e device offers two power-saving features. When addresses have been stable for a specified amount of t im e, the device enters the automatic sleep mode. T h e system can also place the device into the s t a n d by mode. Power consumption is greatly reduced in both modes.
Simultaneous Read/Write Operations with Zero Latency
Th e Simultaneous Read/Write architecture provides s i m u l t a n e o u s operation by dividing the memory space into two banks. The device can improve overall system performance by allowing a host system to prog r a m or erase in one bank, then immediately and simultaneously read from the other bank, with zero lat en cy. This releases the system from waiting for the completion of program or erase operations.
Am29DS323D Features
The Secured Silicon (SecSi) Sector is an additional 64 Kbyte sector capable of being permanently locked by AMD or customers. The SecSi Sector Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable. This way, customer lockable parts can never be used to replace a factory locked part. Fa c t o r y locked parts provide several options. The S e c S i Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (prog ra m m e d through AMD's ExpressFlash service), or both. Customer Lockable parts may utilize the SecSi S ecto r as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing
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Am 2 9 D S 3 2 3 D
PRELIMINARY
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5 Special Handling Instructions for FBGA Package ........... 6 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Am29DS323D Device Bus Operations .......9
Erase Suspend/Erase Resume Commands ... 27
Figure 4. Erase Operation..... 27
Command Definitions .... 28
Table 14. Am29DS323D Command Definitions...... 28
Write Operation Status . . . . . . . . . . . . . . . . . . . . 29 DQ7: Data# Polling ........ 29
Figure 5. Data# Polling Algorithm ........ 29
RY/BY#: Ready/Busy# ... 30 DQ6: Toggle Bit I ........... 30
Figure 6. Toggle Bit Algorithm........ 30
Word/Byte Configuration .......... 9 Requirements for Reading Array Data .... 9 Writing Commands/Command Sequences .... 10
Accelerated Program Operation ......10 Autoselect Functions .....10
DQ2: Toggle Bit II .......... 31 Reading Toggle Bits DQ6/DQ2 ..... 31 DQ5: Exceeded Timing Limits ...... 31 DQ3: Sector Erase Timer ....... 31
Table 15. Write Operation Status ......... 32
Simultaneous Read/Write Operations with Zero Latency ....... 10 Standby Mode ...... 10 Automatic Sleep Mode .. 10 RESET#: Hardware Reset Pin ..... 11 Output Disable Mode ..... 11
Table 2. Am29DS323D Device Bank Divisions .......11 Table 3. Top Boot Sector Addresses (Am29DS32xDT) .........12 Table 4. SecSiTM Sector Addresses for Top Boot Devices .... 13 Table 5. Bottom Boot Sector Addresses (Am29DS32xDB) ...14 Table 6. SecSiTM Sector Addresses for Bottom Boot Devices ....... 15
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 33
Figure 7. Maximum Negative Overshoot Waveform ............ 33 Figure 8. Maximum Positive Overshoot Waveform ..... 33
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 33 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) .... 35 Figure 10. Typical ICC1 vs. Frequency ........... 35
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 11. Test Setup........... 36 Table 16. Test Specifications ......... 36 Figure 12. Input Waveforms and Measurement Levels ........ 36
Autoselect Mode ............ 16
Table 7. Am29DS323D Autoselect Codes (High Voltage Method) 16
Sector/Sector Block Protection and Unprotection ......... 17
Table 8. Top Boot Sector/Sector Block Addresses for Protection/Unprotection ....17 Table 9. Bottom Boot Sector/Sector Block Addresses for Protection/Unprotection ..........17
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 13. Read Operation Timings ..... 37 Figure 14. Reset Timings ...... 38
Word/Byte Configuration (BYTE#) ......... 39
Figure 15. BYTE# Timings for Read Operations.... 39 Figure 16. BYTE# Timings for Write Operations.... 39
Write Protect (WP#) ....... 18 Temporary Sector/Sector Block Unprotect ..... 18
Figure 1. Temporary Sector Unprotect Operation... 18 Figure 2. In-System Sector/Sector Block Protect and Unprotect Algorithms....... 19
Erase and Program Operations .... 40
Figure 17. Program Operation Timings......... Figure 18. Accelerated Program Timing Diagram.. Figure 19. Chip/Sector Erase Operation Timings .. Figure 20. Back-to-back Read/Write Cycle Timings .... Figure 21. Data# Polling Timings (During Embedded Algorithms) . Figure 22. Toggle Bit Timings (During Embedded Algorithms) ...... Figure 23. DQ2 vs. DQ6........ Figure 24. Temporary Sector/Sector Block Unprotect Timing Diagram .... Figure 25. Sector/Sector Block Protect/Unprotect Timing Diagram Figure 26. Alternate CE# Controlled Write (Erase/Program) Operation Timings .... 41 41 42 43 44 45 45 46 47 49
SecSiTM (Secured Silicon) Sector Flash Memory Region ....... 20 Hardware Data Protection ...... 20
Low VCC Write Inhibit ............20 Write Pulse "Glitch" Protection ........21 Logical Inhibit ..........21 Power-Up Write Inhibit ...........21
Common Flash Memory Interface (CFI) . . . . . . . 21
Table 10. CFI Query Identification String ....... 21 Table 11. System Interface String......... 22 Table 12. Device Geometry Definition ........... 22 Table 13. Primary Vendor-Specific Extended Query .... 23
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 24 Reading Array Data ....... 24 Reset Command ............ 24 Autoselect Command Sequence ........... 24 Enter SecSiTM Sector/Exit SecSi Sector Command Sequence ..... 25 Byte/Word Program Command Sequence ..... 25
Unlock Bypass Command Sequence ....25 Figure 3. Program Operation .......... 26
Chip Erase Command Sequence .......... 26 Sector Erase Command Sequence ....... 26
Erase And Programming Performance . . . . . . . 50 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 50 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 FBD048--48-ball Fine-Pitch Ball Grid Array (FBGA) 6 x 12 mm package ....... 51 TS 048--48-Pin Standard TSOP ........... 52 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 53 Revision A (December 1, 1999) .... 53 Publication Number 23480, Revision A (January 25, 2000) ... 53 Revision A+1 (June 16, 2000) ...... 53 Revision A+2 (November 1, 2000) ........ 53 Revision A+3 (November 22, 2000) ...... 53
Am29DS323D
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PRELIMINARY
PRODUCT SELECTOR GUIDE
Part Number Speed Option Max Access Time (ns) CE# Access (ns) OE# Access (ns) Standard Voltage Range: VCC = 1.82.2 V 110 110 110 50 Am29DS323D 120 120 120 50
BLOCK DIAGRAM
VCC VSS
OE# BYTE#
Y-Decoder
A0A20
Upper Bank Address
Upper Bank
Latches and Control Logic
RY/BY#
A0A20 RESET# WE# CE# BYTE# WP#/ACC DQ0DQ15 A0A20 STATE CONTROL & COMMAND REGISTER
X-Decoder
Status DQ0DQ15 Control DQ0DQ15
X-Decoder
Lower Bank
A0A20
Lower Bank Address
OE# BYTE#
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Am 2 9 D S 3 2 3 D
Latches and Control Logic
Y-Decoder
DQ0DQ15
A0A20
PRELIMINARY
CONNECTION DIAGRAMS
A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RESET# NC WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
48-Pin Standard TSOP
Am29DS323D
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