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Part: AM29DS320G
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Company: Advanced Micro Devices, Inc.
Datasheet: Download AM29DS320G datasheet File size : 1483 kB
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Am29DS320G
Data Sheet
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Publication Number 26492 Revision A
Amendment +1 Issue Date January 27, 2003
ADVANCE INFORMATION
Am29DS320G
32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES Simultaneous Read/Write operations -- Data can be continuously read from one bank while executing erase/program functions in another bank -- Zero latency between read and write operations Flexible BankTM architecture -- Read may occur in any of the three banks not being written or erased. -- Four banks may be grouped by customer to achieve desired bank divisions. 256-byte SecSi (Secured Silicon) Sector -- Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data -- Customer lockable: One time programmable. Once locked, data cannot be changed. Zero Power Operation -- Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero Package options -- 48-ball FBGA -- 48-pin TSOP Top or bottom boot blocks Manufactured on 0.17 µm process technology Compatible with JEDEC standards -- Pinout and software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS High performance -- Access time as fast 70 ns -- Program time: 4 µs/word typical utilizing Accelerate function Ultra low power consumption (typical values) -- 2 mA active read current at 1 MHz -- 10 mA active read current at 5 MHz -- 200 nA in standby or automatic sleep mode Minimum 1 million erase cycles guaranteed per sector 20 year data retention at 125°C -- Reliable operation for the life of the system SOFTWARE FEATURES Data Management Software (DMS) -- AMD-supplied software manages data programming, enabling EEPROM emulation -- Eases historical sector erase flash limitations Supports Common Flash Memory Interface (CFI) Erase Suspend/Erase Resume -- Suspends erase operations to allow reading from other sectors in the same bank Data# Polling and Toggle Bits -- Provides a software method of detecting the status of program or erase cycles Unlock Bypass Program command -- Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES Any combination of sectors can be erased Ready/Busy# output (RY/BY#) -- Hardware method for detecting program or erase cycle completion Hardware reset pin (RESET#) -- Hardware method of resetting the internal state machine to the read mode WP#/ACC input pin -- Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status -- Acceleration (ACC) function accelerates program timing Sector protection -- Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector -- Temporary Sector Unprotect allows changing data in protected sectors in-system
This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Publication# 26492 Rev: A Amendment:+1 Issue Date: January 27, 2003
Refer to AMD's Website (www.amd.com) for the latest information.
ADVANCE
INFORMATION
GENERAL DESCRIPTION
The Am29DS320G is a 32 megabit, 1.8 volt-only flash memory device, organized as 2,097,152 words of 16 b i t s each or 4,194,304 bytes of 8 bits each. Word mode data appears on DQ15DQ0; byte mode data a pp ea rs on DQ7DQ0. The device is designed to be programmed in-system with the standard 1.8 volt VCC s u p p l y, and c a n also be programmed in standard EPROM programmers. The device is available with an access time of 70, 90, o r 120 ns. The devices are offered in 48-pin TSOP a n d 48-ball FBGA packages. Standard control pins--chip enable (CE#), write enable (WE#), and output enable (OE#)--control normal read and write operations, and avoid bus contention issues. The device requires only a single 1.8 volt power supply for both read and write functions. Internally genera t e d and regulated voltages are provided for the program and erase operations. Sector. Factory locked parts provide several options. The SecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (prog r a m m e d through AMD's ExpressFlash service), or both. DMS (Data Management Software) allows systems t o remove EEPROM devices. by simplifying system s o f t w a r e : DMS performs all functions necessary to m o d i f y data in file structures, instead of using single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is an advantage comp a r e d to systems where user-written software must ke ep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or memory devices), and more. Using DMS, user-written software does not need to interface with the Flash memory directly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD provides this software to simplify system design and software integration efforts. The device offers complete compatibility with the JED EC single-power-supply Flash command set s t a n d a r d . Commands are written to the command register using standard microprocessor write timings. R e a d i n g data out of the device is similar to reading from other Flash or EPROM devices. T h e host system can detect whether a program or erase operation is complete by using the device stat u s bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to the read mode. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. H ar dware data protection measures include a low V C C detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memo ry. This can be achieved in-system or via programming equipment. T he device offers two power-saving features. When addresses have been stable for a specified amount of t im e , the device enters the automatic sleep mode. T h e system can also place the device into the s t a n d b y mode. Power consumption is greatly reduced in both modes.
Simultaneous Read/Write Operations with Zero Latency
T h e Simultaneous Read/Write architecture provides s i m u l t a n e o u s operation by dividing the memory space into four banks, two 4 Mb banks with small and large sectors, and two 12 Mb banks of large sectors. S ecto r addresses are fixed, system software can be used to form user-defined bank groups. During an Erase/Program operation, any of the three non-busy banks may be read from. Note that only two banks can operate simultaneously. The device allows a host system to program or erase in one bank, then immed ia te ly and simultaneously read from the other bank, with zero latency. This releases the system from w a i t i n g for the completion of program or erase operations. The Am29DS320G can be organized as either a top or bottom boot sector configuration.
Bank Bank 1 Bank 2 Bank 3 Bank 4 Megabits 4 Mb 12 Mb 12 Mb 4 Mb Sector Sizes Eight 8 Kbyte/4 Kword, Seven 64 Kbyte/32 Kword Twenty-four 64 Kbyte/32 Kword Twenty-four 64 Kbyte/32 Kword Eight 64 Kbyte/32 Kword
Am29DS320G Features
T h e SecSiT M (Secured Silicon) Sector is an 256 byte extra sector capable of being permanently locked by AMD or customers. The SecSi Indicator Bit (DQ7) is p er m an en tly set to a 1 if the part is factory locked, a nd set to a 0 if customer lockable. This way, custome r lockable parts can never be used to replace a fa cto ry locked part. Note that some previous AMD 3 2 Mbit Am29DS32x devices had a larger SecSi
2
Am29DS320G
January 27, 2003
ADVANCE
INFORMATION
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Special Package Handling Instructions ......... 5 Unlock Bypass Command Sequence .......... 25
Figure 4. Program Operation ....... 25
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 8
Table 1. Device Bus Operations ....8
Chip Erase Command Sequence ....... 25 Sector Erase Command Sequence .... 26 Erase Suspend/Erase Resume Commands ........ 26
Figure 5. Erase Operation ........... 27 Table 13. Command Definitions .. 28
Write Operation Status . . . . . . . . . . . . . . . . . . . . 29
DQ7: Data# Polling .... 29
Figure 6. Data# Polling Algorithm ......... 29
Word/Byte Configuration ....... 8 Requirements for Reading Array Data ..........8 Writing Commands/Command Sequences ... 9 Accelerated Program Operation .....9 Autoselect Functions .... 9 Simultaneous Read/Write Operations with Zero Latency .........9 Standby Mode ........ 9 Automatic Sleep Mode ..........9 RESET#: Hardware Reset Pin .....10 Output Disable Mode ..........10
Table 2. Top Boot Sector Addresses .........11 Table 3. Top Boot SecSiTM Sector Addresses .... 12 Table 4. Bottom Boot Sector Addresses .....13 Table 5. Bottom Boot SecSiTM Sector Addresses ........ 14
RY/BY#: Ready/Busy# ........ 30 DQ6: Toggle Bit I ........ 30
Figure 7. Toggle Bit Algorithm ..... 30
DQ2: Toggle Bit II ....... 31 Reading Toggle Bits DQ6/DQ2 .... 31 DQ5: Exceeded Timing Limits ...... 31 DQ3: Sector Erase Timer .... 31
Table 14. Write Operation Status ......... 32
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 33
Figure 8. Maximum Negative Overshoot Waveform ..... 33 Figure 9. Maximum Positive Overshoot Waveform ...... 33
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ........... 35 Figure 11. Typical ICC1 vs. Frequency......... 35
Autoselect Mode ........ 15
Table 6. Autoselect Codes, (High Voltage Method) .....15
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 12. Test Setup ........ 36 Figure 13. Input Waveforms and Measurement Levels ...... 36
Sector/Sector Block Protection and Unprotection ...... 16
Table 7. Top Boot Sector/Sector Block Addresses for Protection/Unprotection ..........16 Table 8. Bottom Boot Sector/Sector Block Addresses for Protection/Unprotection ..........16
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 14. Read Operation Timings...... 37 Figure 15. Reset Timings.... 38
Write Protect (WP#) ............17 Temporary Sector Unprotect ........ 17
Figure 1. Temporary Sector Unprotect Operation ......... 17 Figure 2. In-System Sector Protection/ Sector Unprotection Algorithms ... 18
Word/Byte Configuration (BYTE#) ..... 39
Figure 16. BYTE# Timings for Read Operations .......... 39 Figure 17. BYTE# Timings for Write Operations .......... 39
Erase and Program Operations ......... 40
Figure 18. Program Operation Timings ...... Figure 19. Accelerated Program Timing Diagram ........ Figure 20. Chip/Sector Erase Operation Timings ......... Figure 21. Back-to-back Read/Write Cycle Timings ..... Figure 22. Data# Polling Timings (During Embedded Algorithms) ....... Figure 23. Toggle Bit Timings (During Embedded Algorithms) ... Figure 24. DQ2 vs. DQ6 ..... 41 41 42 43 43 44 44
SecSi (Secured Silicon) Sector Flash Memory Region ......... 19 Factory Locked: SecSi Sector Programmed and Protected At the Factory ........19 Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory ..19
Figure 3. SecSi Sector Protect Verify.... 20
TM
Temporary Sector Unprotect ........ 45
Figure 25. Temporary Sector Unprotect Timing Diagram............ 45 Figure 26. Sector/Sector Block Protect and Unprotect Timing Diagram 46
Hardware Data Protection ... 20 Low VCC Write Inhibit ......... 20 Write Pulse "Glitch" Protection .....20 Logical Inhibit .......20 Power-Up Write Inhibit ........20
Alternate CE# Controlled Erase and Program Operations .. 47
Figure 27. Alternate CE# Controlled Write (Erase/Program) Operation Timings ........ 48
Common Flash Memory Interface (CFI) . . . . . . . 21
Table 9. CFI Query Identification String ...... Table 10. System Interface String......... Table 11. Device Geometry Definition ........ Table 12. Primary Vendor-Specific Extended Query .... 21 22 22 23
Erase And Programming Performance . . . . . . . Latchup Characteristics . . . . . . . . . . . . . . . . . . . . TSOP And SO Pin Capacitance . . . . . . . . . . . . . . Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . Physical Dimensions . . . . . . . . . . . . . . . . . . . . . .
49 49 49 49 50
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 23
Reading Array Data .... 23 Reset Command ........ 24 Autoselect Command Sequence ........ 24 Enter SecSiTM Sector/Exit SecSi Sector Command Sequence ..........24 Byte/Word Program Command Sequence ..24
FBD048--Fine-Pitch Ball Grid Array, 6 x 12 mm ....... 50 TS 048--Thin Small Outline Package ......... 51
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 52
Revision A (May 14, 2002) .. 52 Revision A+1 (January 3, 2003) ......... 52
January 27, 2003
Am29DS320G
3
ADVANCE
INFORMATION
PRODUCT SELECTOR GUIDE
Part Number Speed Rating Standard Voltage Range: VCC = 1.82.2 V 70 70 70 30 Am29DS320G 90 90 90 40 120 120 120 50
Max Access Time (ns) CE# Access (ns) OE# Access (ns)
BLOCK DIAGRAM
VCC VSS
OE# BYTE#
Mux A20A0
Bank 1 Address
Bank 1 Y-gate X-Decoder
A20A0
RY/BY#
Bank 2 Address
Bank 2 X-Decoder DQ15DQ0
A20A0 RESET# WE# CE# BYTE# WP#/ACC DQ15DQ0 A20A0 X-Decoder
Bank 3 Address
STATE CONTROL & COMMAND REGISTER
Status DQ15DQ0 Control DQ15DQ0 Mux
Bank 3 Y-gate
X-Decoder A20A0 Mux
Bank 4 Address
Bank 4
4
Am29DS320G
DQ15DQ0
DQ15DQ0
January 27, 2003
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