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Part: AM29DL400BT-70EEB
Category:
Memory
-> Flash
Description: 4 Megabit ( 512 K X 8-bit/256 K X 16-bit ) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
Company: Advanced Micro Devices, Inc.
Datasheet: Download AM29DL400BT-70EEB datasheet File size : 1483 kB
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Datasheet text preview:
PRELIMINARY
Am29DL400B
4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
DISTINCTIVE CHARACTERISTICS
s Simultaneous Read/Write operations -- Host system can program or erase in one bank, then immediately and simultaneously read from the other bank -- Zero latency between read and write operations -- Read-while-erase -- Read-while-program s Single power supply operation -- 2.7 to 3.6 volt read and write operations for battery-powered applications s Manufactured on 0.35 µm process technology s High performance -- Access times as fast as 70 ns s Low current consumption (typical values at 5 MHz) -- 7 mA active read current -- 21 mA active read-while-program or read-whileerase current -- 17 mA active program-while-erase-suspended current -- 200 nA in standby mode -- 200 nA in automatic sleep mode -- Standard tCE chip enable access time applies to transition from automatic sleep mode to active mode s Flexible sector architecture -- Two 16 Kword, two 8 Kword, four 4 Kword, and six 32 Kword sectors in word mode -- Two 32 Kbyte, two 16 Kbyte, four 8 Kbyte, and six 64 Kbyte sectors in byte mode -- Any combination of sectors can be erased -- Suppor ts full chip erase s Unlock Bypass Program Command -- Reduces overall programming time when issuing multiple program command sequences s Sector protection -- Hardware method of locking a sector to prevent any program or erase operation within that sector -- Sectors can be locked in-system or via programming equipment -- Temporar y Sector Unprotect feature allows code changes in previously locked sectors s Top or bottom boot block configurations available s Embedded Algorithms -- Embedded Erase algorithm automatically pre-programs and erases sectors or entire chip -- Embedded Program algorithm automatically programs and verifies data at specified address s Minimum 1 million program/erase cycles guaranteed per sector s Package options -- 44-pin SO -- 48-pin TSOP s Compatible with JEDEC standards -- Pinout and software compatible with single-power-supply flash standard -- Superior inadvertent write protection s Data# Polling and Toggle Bits -- Provides a software method of detecting program or erase cycle completion s Ready/Busy# output (RY/BY#) -- Hardware method for detecting program or erase cycle completion s Erase Suspend/Erase Resume -- Suspends or resumes erasing sectors to allow reading and programming in other sectors -- No need to suspend if sector is in the other bank s Hardware reset pin (RESET#) -- Hardware method of resetting the device to reading array data
Publication# 21606 Rev: C Amendment/0 Issue Date: April 1998
PRELIMINARY
GENERAL DESCRIPTION
T h e Am29DL400B is an 4 Mbit, 3.0 volt-only flash m e m o r y device, organized as 262,144 words or 524,288 bytes. The device is offered in 44-pin SO and 48-pin TSOP packages. The word-wide (x16) data appears on DQ0DQ15; the byte-wide (x8) data appears on DQ0DQ7. This device requires only a single 3.0 volt VCC supply to perform read, program, and erase operations. A standard EPROM programmer can also be used to program and erase the device. The standard device offers access times of 70, 80, 90, and 120 ns, allowing high-speed microprocessors to op erate without wait states. Standard control pins-- chip enable (CE#), write enable (WE#), and output ena ble (OE#)--control read and write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power supply for both read and write functions. Internally genera t e d and regulated voltages are provided for the program and erase operations. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase a lg o r i t h m -- a n internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has be en completed, the device automatically returns to reading array data. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the d a t a contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memor y. This can be achieved in-system or via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector within that bank that is not selected for erasure. True background erase can th u s be achieved. There is no need to suspend the erase operation if the read data is in the other bank. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device to reading array data, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When add re sse s have been stable for a specified amount of tim e, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. AMD's Flash technology combines years of Flash memor y manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte or word at a time using hot electron injection.
Simultaneous Read/Write Operations with Zero Latency
The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into two banks. Bank 1 contains boot/parameter sectors, and Bank 2 consists of larger, code sectors of unifo r m size. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations.
Am29DL400B Features
T h e device offers complete compatibility with the JEDE C single-power-supply Flash command set s t a n d a rd. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state m a c h in e that controls the erase and programming circuitr y. Write cycles also internally latch addresses a n d data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program c o m m a n d sequence. This initiates the Embedded Program algorithm--an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.
2
Am29DL400B
PRELIMINARY
PRODUCT SELECTOR GUIDE
Family Part Number Speed Options (Full Voltage Range: VCC = 2.7 3.6 V) Max Access Time (ns) CE# Access (ns) OE# Access (ns) -70 70 70 30 Am29DL400B -80 80 80 30 -90 90 90 35 -120 120 120 50
Note: See "AC Characteristics" for full specifications.
BLOCK DIAGRAM
VCC VSS OE# BYTE#
Y-Decoder
A0A17
Upper Bank Address
Upper Bank
Latches and Control Logic
RY/BY#
A0A17 RESET# WE# CE# BYTE# DQ0DQ15 A0A17 STATE CONTROL & COMMAND REGISTER Status
X-Decoder
DQ0DQ15
A0A17
DQ0DQ15 Control DQ0DQ15
X-Decoder
Lower Bank
A0A17
Lower Bank Address
OE# BYTE#
Latches and Control Logic
Y-Decoder
21606C-1
Am29DL400B
3
PRELIMINARY
CONNECTION DIAGRAMS
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# NC A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
Standard TSOP
A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Reverse TSOP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# NC A17 A7 A6 A5 A4 A3 A2 A1
21606C-2
4
Am29DL400B
PRELIMINARY
CONNECTION DIAGRAMS
RY/BY# NC A17 A7 A6 A5 A4 A3 A2 A1 A0 CE# VSS OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
SO
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
RESET# WE# A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC
21606C-3
Am29DL400B
5
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